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71. 发明申请

US20080270830A1 Data Processing System and Method for Operating a Data Processing System 有权
标题翻译：数据处理系统和操作数据处理系统的方法
公开(公告)号：US20080270830A1
公开(公告)日：2008-10-30
申请号：US12065454
申请日：2006-07-28
申请人： Reinhhard Weiberle , Eberhard Boehl
发明人： Reinhhard Weiberle , Eberhard Boehl
IPC分类号： G06F11/08
CPC分类号： G06F11/1008 , G11C29/42 , G11C29/52 , G11C2029/0401 , G11C2029/0409 , G11C2029/0411
摘要： To improve the availability of a data processing system despite possible memory errors, when reading a data word from a memory cell, the integrity of the data word is checked on the basis of redundant additional information, and if the data word turns out to be corrupted, an error correction procedure is performed in which the reliability performance of the memory cell is checked and, if the memory cell is found to be operational, its contents are restored.
摘要翻译：为了提高数据处理系统的可用性，尽管存在可能的存储器错误，当从存储器单元读取数据字时，基于冗余附加信息检查数据字的完整性，并且如果数据字被证明已被破坏执行检查存储单元的可靠性的错误校正过程，并且如果存储单元被发现是可操作的，则其内容被恢复。

72. 发明申请

US20080270747A1 Method and Device for Switching Over Between Operating Modes of a Multi-Processor System Using at Least One External Signal 审中-公开
标题翻译：用于在最少一个外部信号上使用多处理器系统的操作模式之间切换的方法和装置
公开(公告)号：US20080270747A1
公开(公告)日：2008-10-30
申请号：US11666325
申请日：2005-10-25
申请人： Wolfgang Pfeiffer , Reinhard Weiberle , Bernd Mueller , Florian Hartwich , Werner Harter , Ralf Angerbauer , Eberhard Boehl , Thomas Kottke , Yorch von Collani , Rainer Gmehlich , Karsten Graebitz
发明人： Wolfgang Pfeiffer , Reinhard Weiberle , Bernd Mueller , Florian Hartwich , Werner Harter , Ralf Angerbauer , Eberhard Boehl , Thomas Kottke , Yorch von Collani , Rainer Gmehlich , Karsten Graebitz
IPC分类号： G06F9/318
CPC分类号： G06F11/1641 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F2201/845
摘要： A method for a switchover in a computer system having at least two execution units, a switchover being performed between at least two operating modes, and a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, wherein the switchover is triggered by at least one signal, which is generated outside the computer system.
摘要翻译：一种用于在具有至少两个执行单元的计算机系统中进行切换的方法，在至少两个操作模式之间执行切换以及对应于比较模式的第一操作模式和对应于演奏模式的第二操作模式，其中，切换由在计算机系统外部生成的至少一个信号触发。

73. 发明申请

US20080270660A1 Method and Device for Switching Over in a Computer System Having at Least Two Execution Units 失效
标题翻译：在具有至少两个执行单元的计算机系统中切换的方法和装置
公开(公告)号：US20080270660A1
公开(公告)日：2008-10-30
申请号：US11666183
申请日：2005-10-25
申请人： Reinhard Weiberle , Bernd Mueller , Yorck von Collani , Rainer Gmehlich , Eberhard Boehl
发明人： Reinhard Weiberle , Bernd Mueller , Yorck von Collani , Rainer Gmehlich , Eberhard Boehl
IPC分类号： G06F13/24
CPC分类号： G06F11/1641 , G06F9/30076 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/3851 , G06F9/3885 , G06F11/1654 , G06F11/1695 , G06F2201/845
摘要： A device and method for switching over in a computer system having at least two execution units are provided, in which switchover units are included which are designed in such a way that they switch between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. A programmable interrupt controller is assigned to each execution unit, and a storage element is included, in which information is stored that describes at least parts of a configuration of at least one of these interrupt controllers.
摘要翻译：提供了一种用于在具有至少两个执行单元的计算机系统中切换的装置和方法，其中包括切换单元，其被设计为使得它们在至少两个操作模式之间切换，第一操作模式对应于比较模式和对应于演奏模式的第二操作模式。可编程中断控制器被分配给每个执行单元，并且包括存储元件，其中存储了至少描述这些中断控制器中的至少一个的配置的一部分的信息。

74. 发明申请

US20060156127A1 Method for transmitting data 有权
标题翻译：发送数据的方法
公开(公告)号：US20060156127A1
公开(公告)日：2006-07-13
申请号：US10534603
申请日：2003-11-06
申请人： Werner Harter , Heikel Zarga , Eberhard Boehl
发明人： Werner Harter , Heikel Zarga , Eberhard Boehl
IPC分类号： G01R31/28
CPC分类号： H04L1/0041
摘要： A method for transmitting data, in which a first signature is formed according to a specifiable signature formation method as a function of the data to be transmitted, the first signature is transmitted together with the data a second signature is formed according to the signature formation method as a function of the transmitted data and the first signature is compared with the second signature. To reduce the likelihood of fault masking in monitoring the transmission of the data using signature analysis, a provision is made to invert the data to be transmitted, to form the first signature according to the specifiable signature formation method as a function of the data to be transmitted and of the inverted Data, to transmit the first signature and the data to invert the transmitted data, to form the second signature acccording to the signature formation method as a function of these inverted data and the transmitted data, and to compare the first signature with the second signature.
摘要翻译：一种用于发送数据的方法，其中根据要发送的数据的函数，根据可指定的签名形成方法形成第一签名，根据签名形成方法将第一签名与数据一起发送第二签名作为发送数据的函数，并将第一签名与第二签名进行比较。为了减少使用签名分析来监视数据的传输的故障屏蔽的可能性，提供反转要发送的数据，根据可指定的签名形成方法形成第一签名作为数据的函数发送和反转数据，以便发送第一签名和数据以反转所发送的数据，根据签名形成方法形成作为这些反转数据和发送数据的函数的第二签名，并将第一签名与第二个签名。

75. 发明授权

US5654708A Process for compensating component tolerances in analog-digital converters 失效
标题翻译：模数转换器补偿元件公差的过程
公开(公告)号：US5654708A
公开(公告)日：1997-08-05
申请号：US535119
申请日：1995-10-26
申请人： Eberhard Boehl , Arnd Gangei , Wilfried Tenten
发明人： Eberhard Boehl , Arnd Gangei , Wilfried Tenten
IPC分类号： H03M1/10 , H03M1/46 , H03M1/80
CPC分类号： H03M1/1033 , H03M1/468 , H03M1/804
摘要： A method for the compensation of component tolerances of a number of similar components, in particular capacitors in analog-to-digital converters which are connected to a common line, and whose electric value is in each case halved from component to component, the component with the smallest value being present twice. In this method, a first potential is at first applied to at least one of the components and a second potential is applied to the remaining components with lower values. A comparator then checks whether on the common line the mid-potential between the two potentials is present. There is then applied to a correction component (which is in addition connected to the common line) a variable correction voltage which is adjusted until the comparator determines the mid-potential on the common line. The determined correction voltage is finally stored as a correction value. As a result, each of these components can be adjusted individually and tolerance errors can be equalized, individual recalibrations being possible in each case which interrupt the converter operation of the analog-to-digital converter only for a very brief period. The precision and linearity of an analog-to-digital converter which uses a capacitor array adjusted in this way are very high.
摘要翻译： PCT No.PCT / DE94 / 00408 Sec。 371 1995年10月26日第 102（e）日期1995年10月26日PCT 1994年4月13日PCT PCT。出版物WO94 / 26034 日期1994年11月10日一种用于补偿多个类似部件的元件公差的方法，特别是连接到公共线的模拟数字转换器中的电容器，并且其电气值在每种情况下从组件到组件组件，具有最小值的组件存在两次。在该方法中，首先将第一电位施加到至少一个部件，并且将第二电位施加到具有较低值的剩余部件。比较器然后检查在公共线上是否存在两个电位之间的中间电位。然后施加到校正分量（其另外连接到公共线路）上的可变校正电压，直到比较器确定公共线路上的中间电位为止。确定的校正电压最终存储为校正值。因此，可以单独调整这些组件中的每一个，并且可以均衡误差，在每一种情况下可以进行单独的重新校准，这样可以在非常短的时间内中断模数转换器的转换器工作。使用以这种方式调节的电容器阵列的模拟 - 数字转换器的精度和线性度非常高。

76. 发明授权

US5629945A Electronic arithmetic unit with multiple error detection 失效
标题翻译：具有多重错误检测功能的电子运算单元
公开(公告)号：US5629945A
公开(公告)日：1997-05-13
申请号：US389707
申请日：1995-02-14
申请人： Peter Sulzberger , Eberhard Boehl
发明人： Peter Sulzberger , Eberhard Boehl
IPC分类号： G06F7/38 , G06F11/10 , G01R31/28 , G06F11/00
CPC分类号： G06F11/104
摘要： An electronic arithmetic unit, such as an ALU, a processor, a controller, or the like, is for the arithmetic gating (combining) of digital operands coded by code bits and supplied via at least one data bus to form data words likewise coded by code bits. The arithmetic gating of the bits of the operands takes place in stages, and in each stage, at least one carry bit is generated. A code-generating unit generates the code bits of the result word from the coded operands while taking into consideration the required operation of the code bits. An additional circuit for duplicated carry generation is assigned to the individual stages. In addition, a testing device is provided for checking the duplicated carry bits for identity. Finally, for each operand, a code checker is provided, which is linked to the individual lines of the at least one data bus via connecting lines, the arithmetic unit and the circuit for duplicated carry generation being connected up between the code checker and the data bus to the connecting lines. In this manner, in addition to faulty operand bits and carry bits, interrupt errors on operand-bit lines can also be detected.
摘要翻译：诸如ALU，处理器，控制器等的电子运算单元用于由码位编码的数字操作数的算术（组合），并经由至少一个数据总线提供，以形成同样由代码位。操作数的位的算术门控分阶段进行，并且在每个阶段中，产生至少一个进位位。代码生成单元在考虑了代码位的所需操作的同时，从编码操作数生成结果字的代码位。用于重复进位生成的附加电路被分配给各个级。此外，提供了用于检查用于身份的重复进位位的测试装置。最后，对于每个操作数，提供代码检查器，其通过连接线链接到至少一个数据总线的各行，运算单元和用于重复进位生成的电路连接在代码检查器和数据之间总线到连接线。以这种方式，除了操作数位和进位位错误之外，还可以检测到操作数位线上的中断错误。

77. 发明授权

US09602109B2 Method and circuit configuration for determining position minus time 有权
公开(公告)号：US09602109B2
公开(公告)日：2017-03-21
申请号：US13637113
申请日：2011-03-16
申请人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
发明人： Eberhard Boehl , Andreas Hempel , Dieter Thoss , Ruben Bartholomae , Stephen Schmitt , Andreas Merker
IPC分类号： H03K99/00 , F02D41/00 , G05B13/02 , F02B3/12 , F02B77/08 , F02D41/40
CPC分类号： H03K99/00 , F02B3/12 , F02B77/087 , F02D41/009 , F02D41/0097 , F02D41/401 , G05B13/026 , G05B2219/2623
摘要： A circuit configuration for a data processing system for predicting a coordinate for at least one operation to be carried out is provided, the prediction being connected to at least one input signal and being a function of a predefined first time value and at least one predefined first value which represents another physical variable. Upon each change of the at least one input signal, a second time value is calculated in each case from the first value, and to subtract the first time value from the second time value to form a third time value, and/or to calculate a second value from the first time value, and to subtract the first value from the second value to form a third value, in order to determine from the third time value and/or the third value a state in which the at least one operation is to be carried out.

78. 发明授权

US09509497B2 Method for generating a random output bit sequence 有权
标题翻译：用于产生随机输出位序列的方法
公开(公告)号：US09509497B2
公开(公告)日：2016-11-29
申请号：US14131134
申请日：2012-06-19
申请人： Eberhard Boehl , Paulius Duplys
发明人： Eberhard Boehl , Paulius Duplys
IPC分类号： H04L9/08 , H04L9/00 , G06F7/58
CPC分类号： H04L9/0816 , G06F7/582 , H04L9/003 , H04L9/004 , H04L2209/24
摘要： A method and a random bit generator for generating a random output bit sequence. In this method, a configuration of 2n state machines is used, the state machines each including n state bits, each state machine always assuming a different state than the other state machines of the configuration, an input signal being supplied to the input end of the state machines, and these each generating n signature bits, which together form a signature bit sequence, as a function of their state, the random output bit sequence being generated by selection of individual bits from the signature bit sequences of all state machines of the configuration.
摘要翻译：一种用于产生随机输出位序列的方法和随机位产生器。在该方法中，使用2n状态机的结构，每个包括n个状态位的状态机，每个状态机总是假定与该配置的其他状态机不同的状态，输入信号被提供给状态机，并且它们每个生成n个签名比特，它们一起形成签名比特序列，作为其状态的函数，通过从配置的所有状态机的签名比特序列中选择各个比特来生成随机输出比特序列。

79. 发明授权

US09436656B2 Method for systematically treating errors 有权
标题翻译：系统地处理错误的方法
公开(公告)号：US09436656B2
公开(公告)日：2016-09-06
申请号：US13637753
申请日：2011-03-16
申请人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
发明人： Eberhard Boehl , Bernd Becker , Bernard Pawlok
IPC分类号： G06F17/00 , G01D5/244 , G01D5/245
CPC分类号： G06F17/00 , G01D5/24452 , G01D5/24471 , G01D5/2449 , G01D5/2457
摘要： A method for systematically handling errors, and an assemblage for carrying out the method, are presented. The method serves for systematically handing errors for a goniometer in the context of the transfer of position data with a position transducer, the position transducer possessing markings that are sensed with at least one sensor; a profile being deposited in a memory region in connection with said markings; the position transducer generating as a function of its position, by way of the markings, position signals that carry, as data, parameters that are deposited into a further memory region beginning with an address pointer value of 0; said address pointer being incremented with each position signal; and a synchronization between the position signals and the profile being created, and the values stored in the profile being used to modify the number of pulses outputted to the goniometer.
摘要翻译：提出了系统地处理错误的方法，以及用于执行该方法的组合。该方法用于在用位置传感器传送位置数据的上下文中系统地处理测角器的误差，位置传感器具有用至少一个传感器感测的标记; 轮廓被沉积在与所述标记相关联的存储区域中; 位置传感器通过标记产生作为其位置的函数的位置信号，作为数据，载入从地址指针值0开始的另外的存储区域中的参数的位置信号; 所述地址指针随每个位置信号递增; 以及位置信号和所创建的轮廓之间的同步，并且存储在轮廓中的值用于修改输出到测角器的脉冲数。

80. 发明授权

US08973006B2 Circuit arrangement for execution planning in a data processing system 有权
标题翻译：用于数据处理系统中执行计划的电路布置
公开(公告)号：US08973006B2
公开(公告)日：2015-03-03
申请号：US13609795
申请日：2012-09-11
申请人： Eberhard Boehl , Ruben Bartholomae
发明人： Eberhard Boehl , Ruben Bartholomae
IPC分类号： G06F9/48 , G06F9/50
CPC分类号： G06F9/4881 , G06F2209/486
摘要： A circuit arrangement and method for a data processing system for executing a plurality of tasks with a central processing unit having a processing capacity allocated to the processing unit; the circuit arrangement being configured to allocate the processing unit to the specific tasks in a time-staggered manner for processing, so that the tasks are processed in an order to be selected and tasks not having a current processing request are skipped over in the order during the processing; the circuit arrangement including a prioritization order control unit to determine the order in which the tasks are executed; and in response to each selection of a task for processing, the order of the tasks being redetermined and the selection being controlled so that for a number N of tasks, a maximum of N time units elapse until an active task is once more allocated processing capacity by the processing unit.
摘要翻译：一种用于使用具有分配给处理单元的处理能力的中央处理单元执行多个任务的数据处理系统的电路装置和方法; 所述电路装置被配置为以时间交错的方式将所述处理单元分配给所述特定任务以进行处理，使得所述任务按照被选择的顺序被处理，并且不具有当前处理请求的任务按照顺序被跳过处理; 所述电路装置包括确定执行任务的顺序的优先顺序控制单元; 并且响应于处理任务的每个选择，所述任务的顺序被重新确定并且所述选择被控制，使得对于N个任务，经过N个时间单位的最多N个单位，直到活动任务再次被分配处理能力由处理单元。

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