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71. 发明授权

US06868082B1 Network processor interface for building scalable switching systems 失效
标题翻译：用于构建可扩展交换系统的网络处理器接口
公开(公告)号：US06868082B1
公开(公告)日：2005-03-15
申请号：US09385603
申请日：1999-08-30
申请人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F13/28 , G06F13/40 , H04L12/28
CPC分类号： G06F13/4022
摘要： A network apparatus comprising storage units storing configuration information about the network apparatus, an input network interface to at least one network physical line, at least one processor receiving network data from said network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units, a first bus interface to two bus connections, a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface, a second bus interface to two bus connections, an output network interface to at least one network physical line, a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage units, said at least one processor reading said formatted data units from said storage units, processing them and sending them as network data to at least one network physical line through said output network interface. On the basis of this network processor, it is possible to build switching systems by adding one network processor and at least one switch; it is also possible to build double density blades attached to two redundant switch fabrics which can also be accessed concurrently.
摘要翻译：一种网络装置，包括存储关于网络装置的配置信息的存储单元，至少一个网络物理线路的输入网络接口，至少一个处理器，从所述网络接口接收网络数据，处理所述数据，将关于所述网络数据的信息存储在所述存储单元，将所述数据作为格式化数据单元存储在所述存储单元中，到两个总线连接的第一总线接口，读取所述配置信息的第一硬件组件和关于存储在所述存储单元中的数据的所述信息，以及控制所存储的所述格式化数据单元所述存储单元到所述第一总线接口的两个总线连接中的至少一个，到两个总线连接的第二总线接口，到至少一个网络物理线的输出网络接口，第二硬件组件读取到达所述第二总线接口的两个总线连接中的至少一个，并存储所述格式化的数据所述至少一个处理器从所述存储单元读取所述格式化的数据单元，处理它们并通过所述输出网络接口将它们作为网络数据发送到至少一个网络物理线路。在该网络处理器的基础上，可以通过添加一个网络处理器和至少一个交换机构建交换系统; 也可以构建连接到两个冗余交换结构的双密度刀片，这两个冗余交换机也可以同时访问。

72. 发明授权

US06842443B2 Network switch using network processor and methods 失效
标题翻译：网络交换机采用网络处理器和方法
公开(公告)号：US06842443B2
公开(公告)日：2005-01-11
申请号：US10002932
申请日：2001-10-23
申请人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/16 , G06F15/177 , H04L12/56 , H04Q3/00 , H04Q3/545 , H04L12/28 , H04B7/216
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样一种设备的方法，其中通过多个接口处理器和形成在半导体衬底上的一组外围元件之间的协作来增强数据流处理和灵活性。接口处理器和外围设备一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选的交换结构设备在内的其他元件进行协作。

73. 发明授权

US06804249B1 Method and system for network processor scheduling based on calculation 失效
标题翻译：基于计算的网络处理器调度方法与系统
公开(公告)号：US06804249B1
公开(公告)日：2004-10-12
申请号：US09548911
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L1256
CPC分类号： H04L47/28 , H04L45/02 , H04L47/2441 , H04L47/50 , H04L2012/5681
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on minimum bandwidth specifications where position in the queue is adjusted after each service based on minimum bandwidth specificaiton and the length of frame, a process which is subject to rounding errors. To avoid the accumulation of rounding errors inequitably influencing the position of some in the queue, a system to adjust for the rounding errors adds an increased measure of fairness to the system.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于基于最小带宽规范来调度来自网络处理单元的处理的信息单元（或帧）的处理的信息单元（或帧），其中基于最小带宽规定在每个服务之后调整队列中的位置，并且帧的长度，一个进行舍入误差的过程。为了避免累积误差不均衡地影响队列中某些队员的位置，调整舍入误差的系统增加了系统的公平性。

74. 发明授权

US06769033B1 Network processor processing complex and methods 失效
标题翻译：网络处理器处理复杂和方法
公开(公告)号：US06769033B1
公开(公告)日：2004-07-27
申请号：US09384691
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Ross Boyd Leavens , Piyush Chunilal Patel , Mark Anthony Rinaldi , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F900
CPC分类号： H04L49/602 , G06F15/80 , H04L49/351
摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.
摘要翻译：可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过嵌入式处理器复合体与一组外围设备的协作来增强数据流处理和灵活性，这些外围设备都形成在公共半导体衬底上。接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成于半导体衬底上的指令存储器中的指令的控制下操作，同时由存储器外围设备和与外部存储器元件的接口提供过渡数据流部分的存储。

75. 发明授权

US06633920B1 Method and system for network data flow management with improved completion unit 失效
标题翻译：网络数据流管理方法与系统改进完成单元
公开(公告)号：US06633920B1
公开(公告)日：2003-10-14
申请号：US09479028
申请日：2000-01-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1300
CPC分类号： H04L29/06 , H04L69/18 , H04L69/22
摘要： A system and method of data flow management, particularly in a multiple network processor architecture where a plurality of independent processing units are simultaneously processing information from different frames of input information. The present invention includes first-in-first-out files identifying the individual frames and correlating the frames with the processor to which the frames have been assigned for processing as well as a first-in-first-out file of processed frames for each processor to allow the frames to be processed independently, then reassembled into the same order as the frames had been received without communication between the independent processors. Additionally, the present system supports newly-created frames as well as the concept of flushing the system without regard to frame order whereby frames are sent out to the network as the processing is completed without regard to input order, overriding the system of putting the output frames in the same order as the input frames were received from the network.
摘要翻译：特别是在多个独立处理单元同时处理来自不同输入信息帧的信息的多网络处理器架构中的数据流管理系统和方法。本发明包括识别各个帧的先进先出文件，并且将帧与已被分配帧进行处理的处理器相关联，以及每个处理器的处理帧的先进先出文件以允许帧被独立地处理，然后重新组装成与已经被接收的帧相同的顺序，而没有独立处理器之间的通信。此外，本系统支持新创建的帧以及刷新系统的概念，而不考虑帧顺序，由此在不考虑输入顺序的情况下处理完成而将帧发送到网络，覆盖输出的系统与从网络接收输入帧相同顺序的帧。

76. 发明授权

US06584518B1 Cycle saving technique for managing linked lists 失效
标题翻译：用于管理链表的循环保存技术
公开(公告)号：US06584518B1
公开(公告)日：2003-06-24
申请号：US09479751
申请日：2000-01-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1314
CPC分类号： G06F12/023
摘要： A method and system for queueing data within a data storage device including a set of storage blocks each having an address, a pointer field, and a data field. This set of storage blocks comprises a linked list of associated storage blocks and also a free pool of available storage blocks. The storage device further includes a tail register for tracking an empty tail block from which a data object is enqueued into the linked list. A request to enqueue a data object into the linked list is received within the data storage system. In response to the data enqueue request, an available storage block from the free pool is selected and associated with the tail register. A single write operation is then required to write the data object into the data field of a current tail block and to write the address of the selected storage block into the pointer field of the current tail block, such that the selected storage block becomes a new tail block to which the tail register points.
摘要翻译：一种用于在数据存储设备内排队数据的方法和系统，包括一组存储块，每个存储块具有地址，指针字段和数据字段。这组存储块包括相关联的存储块的链表以及可用存储块的空闲池。存储装置还包括用于跟踪空尾部块的尾部寄存器，数据对象从该尾部块排入链接列表。在数据存储系统内接收到将数据对象排入链表的请求。响应于数据排入请求，从空闲池中选择一个可用的存储块并将其与尾部寄存器相关联。然后需要单个写入操作来将数据对象写入当前尾部块的数据字段，并将所选择的存储块的地址写入当前尾部块的指针字段，使得所选择的存储块变为新的尾部寄存器指向的尾部块。

77. 发明授权

US06473838B1 Data transfer system for multiple network processors using dual DRAM storage 失效
标题翻译：使用双DRAM存储的多个网络处理器的数据传输系统
公开(公告)号：US06473838B1
公开(公告)日：2002-10-29
申请号：US09477576
申请日：2000-01-04
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1200
CPC分类号： G06F13/1647 , G06F15/167
摘要： The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full ‘read’ and 4 banks of full ‘write’ by the network processor for every repetition of the DRAM time clock. A scheme for randomized ‘read’ and ‘write’ access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.
摘要翻译：网络处理器在计算机系统中使用的动态随机存取存储器（DRAM）芯片中移动数据的能力在几个方面得到了增强。在本发明的一个方面，并行使用两个双数据速率DRAMS以使带宽增加一倍以增加数据吞吐量。数据的移动通过为DRAM时钟的每次重复通过网络处理器设置4组完整“读”和4组完整“写”来进一步改进。公开了一种由网络处理器进行随机“读取”和“写入”访问的方案。该方案特别适用于利用可变帧大小的诸如以太网的网络。

78. 发明授权

US06404752B1 Network switch using network processor and methods 失效
标题翻译：网络交换机采用网络处理器和方法
公开(公告)号：US06404752B1
公开(公告)日：2002-06-11
申请号：US09384747
申请日：1999-08-27
申请人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L1228
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样一种设备的方法，其中通过多个接口处理器和形成在半导体衬底上的一组外围元件之间的协作来增强数据流处理和灵活性。接口处理器和外围设备一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选的交换结构设备在内的其他元件进行协作。

79. 发明授权

US07499470B2 Sequence-preserving deep-packet processing in a multiprocessor system 失效
标题翻译：在多处理器系统中对序列进行深度包处理
公开(公告)号：US07499470B2
公开(公告)日：2009-03-03
申请号：US11963898
申请日：2007-12-24
申请人： Jean Louis Calvignac , Mohammad Pevravian , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Mohammad Pevravian , Fabrice Jean Verplanken
IPC分类号： H04J3/24
CPC分类号： H04L49/9094 , H04L47/10 , H04L47/34 , H04L49/90 , H04L49/9089
摘要： Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.
摘要翻译：数据包或数据帧可以在通过互联网分发之前被压缩，加密/解密，过滤，分类，搜索或经受其他深度包处理操作。本发明的微处理器系统和方法提供这种数据分组的有序处理，而不会中断或改变数据要发送到其目的地的序列。这通过将帧接收到用于处理的输入缓冲器中来实现。与该输入缓冲器相关联的是用于确定要在每个帧上执行的操作的单元。仲裁员将每个帧分配给处理核心引擎。输出缓冲器收集经处理的帧，并且定序器按照输入/输出缓冲器接收的顺序将处理后的帧从输出缓冲区转发到其目的地。保持数据传输的顺序在诸如视频和电影的语音传输中特别有用。

80. 发明授权

US07161961B2 STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 失效
标题翻译： STM-1至STM-64 SDH / SONET成帧器，具有来自一系列可配置I / O端口的数据复用功能
公开(公告)号：US07161961B2
公开(公告)日：2007-01-09
申请号：US09880450
申请日：2001-06-13
申请人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
发明人： Kenneth James Barker , Rolf Clauberg , Jean Louis Calvignac , Andreas Guenther Herkersdorf , Fabrice Jean Verplanken , David John Webb
IPC分类号： H04J3/00 , H04J3/02 , H04L12/56
CPC分类号： H04J3/1611 , H04J3/0685 , H04J3/22 , H04J2203/0089
摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要翻译：本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或根据SDH / SONET标准的STM-N定义更高。此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

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