专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US5459086A Metal via sidewall tilt angle implant for SOG 失效
标题翻译：用于SOG的金属通过侧壁倾斜角植入物
公开(公告)号：US5459086A
公开(公告)日：1995-10-17
申请号：US334953
申请日：1994-11-07
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L21/469 , H01L21/265
CPC分类号： H01L21/76825 , H01L21/76814 , Y10S438/974
摘要： A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer. A large tilt-angle implant is made into the sidewalls of the via openings to transform the exposed spin-on-glass layer so that it will not absorb moisture from the atmosphere thereby preventing outgassing from the intermetal dielectric layer, and thus preventing poisoned via metallurgy. A second metal layer is deposited overlying the intermetal dielectric layer and within the via openings and fabrication of the integrated circuit is completed.
摘要翻译：描述形成集成电路的介电层的新方法。半导体衬底上半导体器件结构上形成厚的绝缘层。第一金属层沉积在厚绝缘层上。使用常规的光刻和蚀刻技术蚀刻第一金属层，以在厚绝缘层的表面上形成所需的金属图案。金属间电介质层通过首先用一层氧化硅覆盖图案化的第一金属层而形成。氧化硅层被被烘烤和固化的旋涂玻璃材料层覆盖。第二层氧化硅完成金属间电介质层。穿过开口通过金属间电介质层形成到下面的图案化的第一金属层。将大的倾斜角植入物制成通孔开口的侧壁，以转化暴露的旋涂玻璃层，使其不会从大气中吸收水分，从而防止从金属间电介质层脱气，从而防止通过冶金中毒。第二金属层沉积在金属间电介质层之上并且在通孔开口内，并且完成了集成电路的制造。

72. 发明授权

US5451534A Method of making single layer thin film transistor static random access memory cell 失效
标题翻译：制造单层薄膜晶体管静态随机存取存储单元的方法
公开(公告)号：US5451534A
公开(公告)日：1995-09-19
申请号：US355656
申请日：1994-12-14
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/1104 , Y10S257/93
摘要： A memory cell layout and method of forming a 6 transistor SRAM memory cell that achieves a reduced cell area using uncomplicated fabrication steps. In one embodiment, a six transistor (6/T) SRAM cell has two horizontal thin-film transistor (T5, T6) as load transistors, two transfer transistors (T1, T2), two latch transistors (T3, T4) and two current nodes (38, 40). In this structure all six transistors are formed in the substrate and a single polysilicon layer.
摘要翻译：一种存储单元布局和形成使用不复杂的制造步骤来实现减小的单元面积的6晶体管SRAM存储单元的方法。在一个实施例中，六晶体管（6 / T）SRAM单元具有两个作为负载晶体管的水平薄膜晶体管（T5，T6），两个传输晶体管（T1，T2），两个锁存晶体管（T3，T4）和两个电流节点（38,40）。在该结构中，所有六个晶体管形成在衬底和单个多晶硅层中。

73. 发明授权

US5449644A Process for contact hole formation using a sacrificial SOG layer 失效
标题翻译：使用牺牲SOG层的接触孔形成方法
公开(公告)号：US5449644A
公开(公告)日：1995-09-12
申请号：US181298
申请日：1994-01-13
申请人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
发明人： Gary Hong , Cheng H. Huang , Ming-Tzong Yang , Hong-Tsz Pan
IPC分类号： H01L21/768 , H01L21/302
CPC分类号： H01L21/76802 , Y10S148/133
摘要： A new method of forming a contact opening by using a sacrificial spin-on-glass layer is described. A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography. A glasseous layer is deposited over the uneven surface of the substrate and reflowed at low temperature whereby the glasseous layer will have a trench shaped surface over the planned contact opening area. The glasseous layer is covered with a spin-on-glass layer wherein the spin-on-glass planarizes the surface of the substrate. The spin-on-glass layer is baked and then covered with a uniform thickness layer of photoresist. The photoresist layer is exposed and developed to form the desired photoresist mask for the contact opening. The exposed spin-on-glass and glasseous layers are etched away to provide the contact opening to the semiconductor substrate. The photoresist layer is stripped and the sacrificial spin-on-glass layer is removed to complete the formation of the contact opening in the manufacture of the integrated circuit.
摘要翻译：描述了通过使用牺牲旋涂玻璃层形成接触开口的新方法。提供半导体衬底，其中衬底的表面具有不平坦的形貌。在基体的不平坦表面上沉积有胶层，并在低温下回流，由此在层叠的接触开口区域上形成沟槽形表面。玻璃层被旋涂玻璃层覆盖，其中旋涂玻璃将基材的表面平坦化。将旋涂玻璃层烘烤，然后用均匀的厚度的光致抗蚀剂层覆盖。光致抗蚀剂层被曝光和显影以形成用于接触开口的所需光刻胶掩模。暴露的旋涂玻璃和玻璃层被蚀刻掉以提供到半导体衬底的接触开口。剥离光致抗蚀剂层，去除牺牲旋涂玻璃层，以在集成电路的制造中完成接触开口的形成。

74. 发明授权

US5436190A Method for fabricating semiconductor device isolation using double oxide spacers 失效
标题翻译：使用双氧化物间隔物制造半导体器件隔离的方法
公开(公告)号：US5436190A
公开(公告)日：1995-07-25
申请号：US344007
申请日：1994-11-23
申请人： Ming-Tzong Yang , Chung-Cheng Wu
发明人： Ming-Tzong Yang , Chung-Cheng Wu
IPC分类号： H01L21/763 , H01L21/76
CPC分类号： H01L21/763
摘要： A method for fabricating a very narrow electrical isolation trench in a semiconductor substrate for isolating the individual field effect transistors (FETs) is achieved. This method eliminates the oxide encroachment into the device area associated with LOCOS techniques, thereby increasing device density. The method involves etching trenches, less than one half micrometer in width in the silicon substrate and forming sidewall spacer in the trench. The trench is filled with doped polysilicon and planarized, forming a trench which is planar with the device region. These isolation trenches are made in both N and P-wells for fabricating CMOS circuits having ULSI densities.
摘要翻译：实现了用于在用于隔离各个场效应晶体管（FET）的半导体衬底中制造非常窄的电隔离沟槽的方法。该方法消除了与LOCOS技术相关的器件区域的氧化物侵蚀，从而增加器件密度。该方法包括蚀刻在硅衬底中宽度小于半微米的沟槽，并在沟槽中形成侧壁间隔物。沟槽填充有掺杂的多晶硅并且被平坦化，形成与器件区域平坦的沟槽。这些隔离沟槽在N阱和P阱中制造，用于制造具有ULSI密度的CMOS电路。

75. 发明授权

US5436186A Process for fabricating a stacked capacitor 失效
标题翻译：叠层电容器制造工艺
公开(公告)号：US5436186A
公开(公告)日：1995-07-25
申请号：US231516
申请日：1994-04-22
申请人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Gary Hong , Ming-Tzong Yang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for fabricating a capacitors having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric. The top capacitor electrode is formed by depositing a doped polysilicon layer which also fills the recesses in the bottom electrode forming an interdigitized fin-shaped top and bottom capacitor electrodes and completing a dynamic random access memory (DRAM) cell.
摘要翻译：实现了在具有增加的电容的动态随机存取存储器（DRAM）单元上制造具有鳍状电极的电容器的方法。电容器制造在具有有源器件区域的硅衬底上。器件区域包含一个金属氧化物半导体场效应晶体管（MOSFET），其中一个电容器对准器件区域中与MOSFET的源极/漏极对准并接触。通过在存储电容器区域和凹陷交替层上形成多层绝缘体结构，然后使用该形式作为形成多晶硅鳍状底部电容器电极的模具，电容器增加电容。去除剩余的多层模具，并且在底部电极上沉积高介电常数绝缘体作为电极间电介质。顶部电容器电极通过沉积掺杂的多晶硅层而形成，掺杂多晶硅层还填充底部电极中的凹部，形成交错的鳍状顶部和底部电容器电极并完成动态随机存取存储器（DRAM）单元。

76. 发明授权

US5393233A Process for fabricating double poly high density buried bit line mask ROM 失效
标题翻译：双重高密度掩埋位线掩模ROM的制造工艺
公开(公告)号：US5393233A
公开(公告)日：1995-02-28
申请号：US92190
申请日：1993-07-14
申请人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
发明人： Gary Hong , Ming-Tzong Yang , Chen-Chiu Hsue
IPC分类号： H01L21/8246 , H01L21/70
CPC分类号： H01L27/1126
摘要： In accordance with the invention, a double poly process is used to double the memory density of a buried bit line ROM on the same silicon area. In particular the word-line pitch is decreased to increase the cell density in a direction perpendicular to the word lines. The invention uses a self-aligned method for ROM code implantation and a polyplanarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure.
摘要翻译：根据本发明，双重多晶法用于将相同硅区上的掩埋位线ROM的存储密度加倍。特别地，减小字线间距以在垂直于字线的方向上增加单元密度。本发明采用自对准方法进行ROM码植入和通过化学机械抛光（CMP）进行多平面化，以实现自对准双多重字线结构。

77. 发明授权

US5366918A Method for fabricating a split polysilicon SRAM cell 失效
标题翻译：分离多晶硅SRAM单元的制造方法
公开(公告)号：US5366918A
公开(公告)日：1994-11-22
申请号：US192366
申请日：1994-02-07
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70
CPC分类号： H01L27/1108 , H01L27/11 , H01L27/1112 , Y10S257/90 , Y10S257/904
摘要： An SRAM semiconductor device comprises a first layer, a second layer and a third layer of polysilicon are separated by dielectric layers formed on a substrate, and a split gate structure with transistors formed in different polysilicon levels. Preferably, the split gate structure includes pull down transistors and pass gate transistors formed in different polysilicon levels; the second polysilicon layer extends into contact with the substrate; the second polysilicon layer contacts the third polysilicon layer in an interconnection region; and the third polysilicon layer comprises a polysilicon load resistor.
摘要翻译：包括第一层，第二层和第三多晶硅层的SRAM半导体器件由形成在衬底上的电介质层分离，并且具有以不同多晶硅层形成的晶体管的分离栅极结构。优选地，分离栅极结构包括形成在不同多晶硅层中的下拉晶体管和栅极晶体管; 第二多晶硅层延伸成与基板接触; 第二多晶硅层在互连区域中接触第三多晶硅层; 并且第三多晶硅层包括多晶硅负载电阻器。

78. 发明授权

US5318921A Method for making a high density ROM or EPROM integrated circuit 失效
标题翻译：制造高密度ROM或EPROM集成电路的方法
公开(公告)号：US5318921A
公开(公告)日：1994-06-07
申请号：US55867
申请日：1993-05-03
申请人： Chen-Chiu Hsue , Ming-Tzong Yang
发明人： Chen-Chiu Hsue , Ming-Tzong Yang
IPC分类号： H01L21/768 , H01L21/8246 , H01L21/70 , H01L27/00
CPC分类号： H01L27/1122 , H01L21/768
摘要： An insulating layer structure is formed over semiconductor device structures in and on a semiconductor substrate. A conductive polysilicon layer covers the insulating layer which is covered by a silicon oxide layer. The oxide layer is now patterned by lithography and etching. This patterning leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form closely spaced polysilicon conductor lines. The silicon oxide layers over the polysilicon conductor lines are removed as by etching. N+ ions are implanted into the silicon substrate under the spacing between the polysilicon conductor lines to form bit lines. An insulating layer structure is formed over the bit lines. Processing continues as before to form a second set of polysilicon lines which form the word lines.
摘要翻译：半导体衬底上半导体器件结构上形成绝缘层结构。导电多晶硅层覆盖被氧化硅层覆盖的绝缘层。氧化层现在通过光刻和蚀刻图案化。该图案在第一指定的多个多晶硅导体线上留下氧化物的第一图案，并且在第二指定的多个多晶硅导体线之间暴露多晶硅层的氧化物加上第一和第二多晶硅导体线之间的预定间隔多晶硅导线。在氧化物层和暴露的多晶硅层上沉积均匀的厚度的氮化硅层，其中厚度是预定间距的宽度。氮化物层被各向异性蚀刻以产生具有预定间隔宽度的侧壁结构。暴露的多晶硅层被氧化。通过蚀刻去除侧壁结构。暴露的多晶硅层被各向异性蚀刻以形成紧密间隔的多晶硅导体线。通过蚀刻去除多晶硅导体线上的氧化硅层。在多晶硅导体线之间的间隔处将N +离子注入到硅衬底中以形成位线。在位线上形成绝缘层结构。处理如前所述继续形成形成字线的第二组多晶硅线。

79. 发明授权

US06232215B1 Method for forming increased density for interconnection metallization 失效
标题翻译：用于形成互连金属化增加密度的方法
公开(公告)号：US06232215B1
公开(公告)日：2001-05-15
申请号：US08931235
申请日：1997-09-15
申请人： Ming-Tzong Yang
发明人： Ming-Tzong Yang
IPC分类号： H01L214763
CPC分类号： H01L21/76885
摘要： A layer of metal is deposited on the surface of a layer of dielectric material and layer of protective material such as a thin layer of silicon oxide is provided on the layer of metal. An etch mask, which might be photoresist, is provided on the layer of protective material. The protective layer is etched through and the metal layer is etched using the photoresist etch mask. Little or no overetching is performed at this time, so it is likely that stringers from the metal layer will be left between the patterned wiring lines. Sidewall structures are then formed alongside the metal lines to protect the sidewalls of the wiring lines from undercutting and corrosion in subsequent etching steps. Overetching is then performed to remove any metal stringers, with the protective layer and the sidewall structures acting as masks for the overetching process, protecting the wiring lines from thinning during this etch process.
摘要翻译：一层金属沉积在介电材料层的表面上，并且在金属层上提供诸如氧化硅薄层的保护材料层。可以在防护材料层上提供可能是光致抗蚀剂的蚀刻掩模。蚀刻保护层，并使用光致抗蚀剂蚀刻掩模蚀刻金属层。此时很少或没有进行过蚀刻，因此可能来自金属层的桁条将留在图案化的布线之间。然后在金属线旁边形成侧壁结构，以保护布线的侧壁在随后的蚀刻步骤中防止底切和腐蚀。然后进行过蚀刻以除去任何金属纵梁，其中保护层和侧壁结构充当用于过蚀刻工艺的掩模，从而在该蚀刻工艺期间保护布线不变薄。

80. 发明授权

US06221731B1 Process of fabricating buried diffusion junction 失效
标题翻译：制造掩埋扩散结的工艺
公开(公告)号：US06221731B1
公开(公告)日：2001-04-24
申请号：US09063022
申请日：1998-04-20
申请人： Nai-Chen Peng , Ming-Tzong Yang
发明人： Nai-Chen Peng , Ming-Tzong Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/76213
摘要： A process is disclosed for fabricating buried diffusion junction that can be combined with the shallow-trench isolation for the memory device cell unit transistor wherein both the junction and the isolation can be formed in the same layout. The buried diffusion is free from being inadvertently cut apart to cause open-circuiting. A bird's beak oxide layer is formed protecting the buried diffusion junction region from undesirable etching, thereby preventing from damaging consumption by etching. The buried diffusion junctions formed may serve as the source/drain region for the transistor.
摘要翻译：公开了一种用于制造掩埋扩散结的方法，其可以与用于存储器件单元晶体管的浅沟槽隔离组合，其中结和隔离可以以相同的布局形成。埋入的扩散层不会被无意间切开，导致开路。形成鸟的喙状氧化物层，以保护掩埋的扩散连接区域免受不希望的蚀刻，从而防止蚀刻损耗。所形成的掩埋扩散结可以用作晶体管的源极/漏极区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式