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71. 发明申请

US20070051638A1 Electropolishing liquid, electropolishing method, and method for fabricating semiconductor device 审中-公开
标题翻译：电抛光液，电解抛光方法及制造半导体器件的方法
公开(公告)号：US20070051638A1
公开(公告)日：2007-03-08
申请号：US11591688
申请日：2006-11-01
申请人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
发明人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
IPC分类号： B23H5/00
CPC分类号： C09G1/02 , C25F3/02 , C25F3/16 , H01L21/32125
摘要： Electric conductivity is enhanced without causing coagulation or precipitation of polishing abrasive grains. In addition, good planarization is realized without inducing defects in a metallic film or a wiring which are to be polished. In an electropolishing method for planarizing the surface of a metallic film to be polished by moving a polishing pad (15) in sliding contact with the metallic film surface while oxidizing the metallic film surface through an electrolytic action in an electropolishing liquid E, the electropolishing liquid E contains at least polishing abrasive grains and an electrolyte for maintaining an electrostatically charged state of the polishing abrasive grains. Since the electropolishing liquid having a high electric conductivity is used, it is possible to obtain a high electrolyzing current and to enlarge the distance between electrodes. Besides, in the electropolishing method, the electropolishing liquid with a good dispersion state of the polishing abrasive grains is used, so that remaining of the abrasive grains and defects such as scratches are prevented from being generated upon polishing.
摘要翻译：电导率提高而不引起研磨磨粒的凝结或沉淀。此外，实现良好的平坦化，而不会引起要抛光的金属膜或布线的缺陷。在电抛光方法中，通过在电解抛光液体E中通过电解作用使金属膜表面氧化而移动与金属膜表面滑动接触的抛光垫（15）来平坦化待抛光的金属膜的表面，电抛光液 E至少含有抛光磨粒和用于保持抛光磨粒的静电充电状态的电解质。由于使用具有高导电性的电解抛光液体，因此可以获得高的电解电流并且扩大电极之间的距离。此外，在电抛光方法中，使用具有抛光磨粒的良好分散状态的电解抛光液，从而防止在研磨时残留磨粒和划痕等缺陷。

72. 发明授权

US07156975B2 Polishing method and electropolishing apparatus 有权
标题翻译：抛光方法和电抛光装置
公开(公告)号：US07156975B2
公开(公告)日：2007-01-02
申请号：US10304174
申请日：2002-11-26
申请人： Shuzo Sato , Takeshi Nogami , Zenya Yasuda , Masao Ishihara
发明人： Shuzo Sato , Takeshi Nogami , Zenya Yasuda , Masao Ishihara
IPC分类号： C25F3/16 , C25F7/00 , B23H5/06 , B23H3/02 , C25F3/22
CPC分类号： B24B37/013 , B24B49/04 , B24B49/10
摘要： A polishing method for electropolishing a metal film formed on a wafer surface so as to fill concave portions formed on the wafer surface comprises a step of determining an electropolishing end point of the metal film on the basis of a change of a current waveform resulting from electropolishing the metal film. An electropolishing apparatus comprising a current detector for detecting a current waveform resulting from electropolishing a metal film and an end point determination part for determining an electropolishing end point of the metal film on the basis of the change of a current detected with the current detector is used to realize the polishing method.
摘要翻译：电抛光形成在晶片表面上以形成在晶片表面上的凹部的金属膜的抛光方法包括基于电抛光产生的电流波形的变化来确定金属膜的电抛光终点的步骤金属膜。使用电抛光装置，其包括用于检测由电解抛光金属膜产生的电流波形的电流检测器和用于基于由电流检测器检测的电流变化来确定金属膜的电抛光终点的终点确定部件实现抛光方法。

73. 发明申请

US20060183345A1 ADVANCED LOW DIELECTRIC CONSTANT ORGANOSILICON PLASMA CHEMICAL VAPOR DEPOSITION FILMS 有权
标题翻译：高级低介电常数有机硅等离子体化学气相沉积膜
公开(公告)号：US20060183345A1
公开(公告)日：2006-08-17
申请号：US10906370
申请日：2005-02-16
申请人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
发明人： Son Nguyen , Sarah Lane , Jia Lee , Kensaku Ida , Darryl Restaino , Takeshi Nogami
IPC分类号： H01L21/31
CPC分类号： H01L21/7682 , C23C16/401 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/0234 , H01L21/02348 , H01L21/02351 , H01L21/02354 , H01L21/3122 , H01L21/31633 , H01L2221/1047
摘要： A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.
摘要翻译：在介电常数小于约3.0的共价键合的三维网络结构中，包含Si，C，O和H原子（以下称为“SiCOH”）的多孔低k或超低k电介质膜，结晶度更高键合相互作用，提供比现有技术的SiCOH电介质更多的碳作为甲基端基和较少的亚甲基-CH 2 - 2交联基团。 SiCOH电介质的特征在于具有包含小于约1.40的CH 3 N 2 CH 2拉伸的峰面积的FTIR光谱，SiH拉伸的峰面积小于约0.20，SiCH 3键的峰面积大于约2.0，Si-O-Si键合的峰面积大于约60％，孔隙率大于约20％。

74. 发明申请

US20050224368A1 Polishing system and polishing method 审中-公开
标题翻译：抛光系统和抛光方法
公开(公告)号：US20050224368A1
公开(公告)日：2005-10-13
申请号：US10512185
申请日：2003-04-14
申请人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
发明人： Shuzo Sato , Takeshi Nogami , Shingo Takahashi , Naoki Komai , Kaori Tai , Hiroshi Horikoshi , Hiizu Ohtorii
IPC分类号： B23H5/06 , B24B53/00 , B24B53/007 , C25F3/16 , H01L21/321 , B23H5/02
CPC分类号： B24B53/017 , B24B53/001 , C25F3/16 , H01L21/32125
摘要： A polishing apparatus and a polishing method by which it is possible to restrain variations in the composition of an electrolytic solution 2 between a wafer 3 and a counter electrode 5, and the like, and to make current density distribution substantially constant in the plane of the wafer. The polishing apparatus, for planarizing a surface to be polished 3a by electrolytic combined polishing composed of a combination of electropolishing and mechanical polishing, includes a voltage impressing means 5 disposed oppositely to the surface to be polished 3a, and a discharging means for discharging foreign matter intermediately present between the voltage impressing means 5 and the object of polishing.
摘要翻译：可以抑制晶片3和对电极5之间的电解液2的组成变化等的抛光装置和抛光方法，并使电流密度分布在晶圆。用于通过电抛光和机械抛光组合的电解组合抛光来平坦化待抛光表面3a的抛光装置包括与待抛光表面3a相对设置的电压施加装置5，以及用于放电的放电装置电压施加装置5和抛光对象之间中间存在异物。

75. 发明授权

US06911396B2 Method of producing metallic film 失效
标题翻译：金属膜的制造方法
公开(公告)号：US06911396B2
公开(公告)日：2005-06-28
申请号：US10469580
申请日：2002-12-27
申请人： Shuzo Sato , Takeshi Nogami , Yuji Segawa
发明人： Shuzo Sato , Takeshi Nogami , Yuji Segawa
IPC分类号： C25D5/48 , C25D7/12 , C25F3/22 , H01L21/28 , H01L21/288 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/311 , H01L21/20 , H01L21/461
CPC分类号： H01L21/76877 , C25D5/48 , C25D7/12 , C25F3/22 , H01L21/2885 , H01L21/7684
摘要： Concentration of electric current due to an additive (particularly, a brightener) remaining or precipitated in a high concentration at grain boundary triple points and wiring groove portions in the surface layer of a copper plating film is obviated, whereby precedent dissolution and/or abnormal dissolution due to concentration of electric current is restrained, and an electropolished surface of the copper plating film with excellent surface smoothness is obtained.A method of producing a metallic film includes the steps of: forming a metallic plating film (copper plating film (15)) by use of a plating solution prepared by adding a plating additive for restraining void generation, bottom-up fill and overfill; and electropolishing the metallic plating film by use of an electropolishing solution prepared by adding a polishing additive capable of reacting or coupling with the plating additive component contained or precipitated in the surface layer of the metallic plating film.
摘要翻译：避免了由于在镀铜膜的表面层中的晶界三点和布线槽部分处高浓度地残留或沉淀的添加剂（特别是增白剂）导致的电流浓度，从而导致先前的溶解和/或异常溶解由于电流的集中受到抑制，并且获得了具有优异表面平滑度的镀铜膜的电抛光表面。制造金属膜的方法包括以下步骤：通过使用通过添加用于抑制空洞产生的电镀添加剂，自底向上填充和填充填充而制备的电镀液，形成金属镀膜（镀铜膜（15））。并使用通过添加能够与包含或沉淀在金属镀膜的表面层中的镀覆添加剂成分反应或偶合的抛光添加剂而制备的电解抛光溶液电抛光金属镀膜。

76. 发明授权

US06809029B2 Semiconductor production device and production method for semiconductor device 失效
标题翻译：半导体装置的半导体制造装置及其制造方法
公开(公告)号：US06809029B2
公开(公告)日：2004-10-26
申请号：US10149858
申请日：2002-10-07
申请人： Takeshi Nogami , Naoki Komai
发明人： Takeshi Nogami , Naoki Komai
IPC分类号： H01L214763
CPC分类号： H01L21/67167 , B24B37/04 , C25D7/123 , C25D17/001 , H01L21/67219 , H01L21/6723
摘要： The present invention provides a semiconductor manufacturing apparatus capable of shortening TAT by completing a plurality of processes including plating, annealing, and CMP-in-twice or the like in copper wiring process in a single manufacturing apparatus, and is also capable of suppressing costs for consumable materials by replacing the CMP step with other step. The apparatus of the present invention comprises an electrolytic plating chamber (11) for performing electrolytic plating of a substrate (91), an electrolytic polishing chamber (21) for performing electrolytic polishing of the substrate, and a conveying chamber (81) having installed therein a conveying instrument (83) responsible for loading/unloading of the substrate to or from the electrolytic plating chamber, and to or from he electrolytic polishing chamber, and is connected respectively to the electrolytic plating chamber and the electrolytic polishing chamber. The conveying chamber may further have connected thereto an electroless plating chamber, an annealing chamber, a liquid treatment chamber or the like.
摘要翻译：本发明提供一种半导体制造装置，其能够通过在单个制造装置中的铜布线工序中完成包括电镀，退火和CMP二次等的多个处理来缩短TAT，并且还能够抑制成本通过用其他步骤代替CMP步骤来消耗材料。本发明的装置包括用于进行基板（91）的电解电镀的电解电镀室（11），用于对基板进行电解抛光的电解抛光室（21），以及安装在其中的输送室负责将基板装载到电解电镀室和从电解电镀室进行加载/卸载的输送装置（83），并且分别与电解电镀室和电解研磨室连接。输送室还可以连接有无电镀室，退火室，液体处理室等。

77. 发明授权

US06797623B2 Methods of producing and polishing semiconductor device and polishing apparatus 失效
标题翻译：半导体器件和抛光装置的制造和抛光方法
公开(公告)号：US06797623B2
公开(公告)日：2004-09-28
申请号：US09800580
申请日：2001-03-08
申请人： Shuzo Sato , Yuji Segawa , Akira Yoshio , Hiizu Ootorii , Zenya Yasuda , Masao Ishihara , Takeshi Nogami , Naoki Komai
发明人： Shuzo Sato , Yuji Segawa , Akira Yoshio , Hiizu Ootorii , Zenya Yasuda , Masao Ishihara , Takeshi Nogami , Naoki Komai
IPC分类号： H01L21302
CPC分类号： B24B37/042 , B23H5/08 , B24B37/046 , B24B37/16 , B24B37/26 , C25F3/30 , C25F7/00 , H01L21/3212 , H01L21/32125 , H01L21/7684 , H01L21/76843
摘要： A method of production and a method of polishing a semiconductor device and a polishing apparatus, capable of easily flattening an initial unevenness of a metal film, excellent in efficiency of removal of an excess metal film, and capable of suppressing damage to an interlayer insulation film below the metal film when flattening the metal film by polishing, the polishing method including the steps of interposing an electrolytic solution including a chelating agent between a cathode member and the copper film, applying a voltage between the cathode member used as a cathode and the copper film used as an anode to oxidize the surface of the copper film and forming a chelate film of the oxidized copper, selectively removing a projecting portion of the chelate film corresponding to the shape of the copper film to expose the projecting portion of the copper film at its surface, and repeating the above chelate film forming step and the above chelate film removing step until the projecting portion of the copper film is flattened.
摘要翻译：一种生产方法和抛光半导体器件和抛光装置的方法，其能够容易地平坦化金属膜的初始不均匀性，除去过量金属膜的效率优异，并且能够抑制对层间绝缘膜的损伤在通过抛光使金属膜平坦化时，金属膜下方的抛光方法包括以下步骤：在阴极构件和铜膜之间插入包含螯合剂的电解液，在用作阴极的阴极构件和铜膜用作氧化铜膜的表面并形成氧化铜的螯合膜，选择性地除去与铜膜形状相对应的螯合膜的突出部分，以暴露铜膜的突出部分并重复上述螯合膜形成步骤和上述螯合膜去除步骤，直到突出使铜膜变平。

78. 发明授权

US06563222B1 Method and apparatus for reducing electromigration in semiconductor interconnect lines 有权
标题翻译：用于减少半导体互连线路中的电迁移的方法和装置
公开(公告)号：US06563222B1
公开(公告)日：2003-05-13
申请号：US09999703
申请日：2001-10-24
申请人： Takeshi Nogami , Sergey Lopatin
发明人： Takeshi Nogami , Sergey Lopatin
IPC分类号： H01L2348
CPC分类号： H01L21/76877 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： A method for making a semiconductor chip includes disposing copper interconnects adjacent via channels and then doping only the portions of the interconnects that lie directly beneath the via channels. Then, the via channels are filled with electrically conductive material. The impurities with which the interconnects are locally doped reduce unwanted electromigration of copper atoms at the interconnect-via interfaces, while not unduly increasing line resistance in the interconnects.
摘要翻译：一种用于制造半导体芯片的方法包括：经由沟道邻近布置铜互连，然后仅掺杂直接位于通孔通道下方的互连部分。然后，通孔通道填充有导电材料。局部掺杂互连的杂质减少了互连通孔界面处铜原子的不必要的电迁移，同时不会过度增加互连中的线电阻。

79. 发明授权

US06368961B1 Graded compound seed layers for semiconductors 有权
标题翻译：半导体分级复合种子层
公开(公告)号：US06368961B1
公开(公告)日：2002-04-09
申请号：US09723812
申请日：2000-11-28
申请人： Sergey D. Lopatin , Takeshi Nogami
发明人： Sergey D. Lopatin , Takeshi Nogami
IPC分类号： H01L2124
CPC分类号： H01L21/76871 , H01L21/76843 , H01L21/76873 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming semiconductor copper seed layers with the copper alloyed with one of the metals from the group comprising tin, magnesium, and aluminum. The alloy further has a graded nitrogen content with the highest concentration of nitrogen proximate a tungsten nitride barrier layer. The high concentration of nitrogen in the copper alloy provides good adhesion of the seed layer to the barrier layer while the lack of nitrogen away from the barrier layer allows the copper conductive to have good adhesion with the pure copper conductive material.
摘要翻译：提供了一种形成半导体铜种子层的方法，其中铜与由锡，镁和铝组成的组中的一种合金化。该合金还具有氮化氮阻挡层附近氮浓度最高的氮。铜合金中的高浓度氮提供了种子层与阻挡层的良好粘附性，而阻挡层的氮缺乏使得铜导电体与纯铜导电材料具有良好的粘合性。

80. 发明授权

US06214731B1 Copper metalization with improved electromigration resistance 有权
标题翻译：铜金属化具有改善的电迁移率
公开(公告)号：US06214731B1
公开(公告)日：2001-04-10
申请号：US09442771
申请日：1999-11-18
申请人： Takeshi Nogami , Minh Van Ngo , Shekhar Pramanick
发明人： Takeshi Nogami , Minh Van Ngo , Shekhar Pramanick
IPC分类号： H01L2144
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.
摘要翻译：具有改善的电迁移电阻的Cu互连图案通过沉积阻挡金属层（例如W或WN）来形成，以对电介质层中的开口进行排列。沉积的阻挡金属层的暴露表面用硅烷或二氯苯胺处理以在其上形成薄硅层。然后沉积Cu以填充开口并与薄硅层反应以在Cu和阻挡金属层之间的界面处形成Cu硅化物的薄层，从而降低界面缺陷密度并提高电迁移阻力。

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