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71. 发明申请

US20120295453A1 TALL MEZZANINE CONNECTOR 失效
标题翻译：甲醇连接器
公开(公告)号：US20120295453A1
公开(公告)日：2012-11-22
申请号：US13108955
申请日：2011-05-16
申请人： Thomas M. Cipolla , Paul W. Coteus , Todd Takken
发明人： Thomas M. Cipolla , Paul W. Coteus , Todd Takken
IPC分类号： H01R12/79 , H05K1/09
CPC分类号： H05K1/144 , H01R12/716 , H01R12/73 , H01R12/79 , H05K1/0219 , H05K1/0245 , H05K1/118 , H05K1/147 , H05K2201/10189
摘要： A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto. The mezzanine connector comprises a and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.
摘要翻译：一个高夹层连接器，连接一对位于其上的一对电路卡的每个的大致中间的一半。夹层连接器包括一个和一个插座，其包括在其每个端部具有电接触装置的晶片，用于接触各个电路卡中的触点，晶片通过上部基座构件和下部基座构件保持就位。

72. 发明授权

US08307270B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08307270B2
公开(公告)日：2012-11-06
申请号：US12553400
申请日：2009-09-03
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G11C29/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的先进内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

73. 发明授权

US08174106B2 Through board stacking of multiple LGA-connected components 有权
公开(公告)号：US08174106B2
公开(公告)日：2012-05-08
申请号：US11511815
申请日：2006-08-29
申请人： Paul W. Coteus , Shawn A. Hall , Gareth G. Hougham , Alphonso P. Lanzetta , Rick A. Rand
发明人： Paul W. Coteus , Shawn A. Hall , Gareth G. Hougham , Alphonso P. Lanzetta , Rick A. Rand
IPC分类号： H01L23/02
CPC分类号： H05K3/325 , H05K2201/0314 , H05K2201/10545 , H05K2201/10719 , H05K2201/2018
摘要： A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.

74. 发明授权

US08171630B2 Method of producing a land grid array interposer 有权
标题翻译：地面栅格阵列插入器的制作方法
公开(公告)号：US08171630B2
公开(公告)日：2012-05-08
申请号：US12047603
申请日：2008-03-13
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R43/16
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure includes mounting at least one interposer on a first surface of an electrically insulating carrier plane. The interposer selectively having a hemi-toroidal, conical, dome-shaped conic section, generally cylindrical or hemi-spherical configuration in transverse cross-section and being constituted of a dielectric elastomeric material. The method includes positioning a plurality of electrically-conductive elements about the surface of the hemi-toroidal interposer that extend radially inwardly and downwardly from an uppermost end thereof. The method further includes mounting said at least one component comprising at least one hemi-toroidal interposer mounted on said opposite side of said carrier plane. Additionally the method includes forming at least one through-extending via in said electrically-insulating carrier plane, and forming electrical connections between said first-mentioned at least one hemi-toroidal interposer and said further at least one inverted hemi-toroidal interposer.
摘要翻译：一种制造焊盘格栅阵列（LGA）插入器结构的方法包括在电绝缘载体平面的第一表面上安装至少一个插入件。中间层选择性地具有半环形，圆锥形的圆顶形圆锥形截面，横截面为大致圆柱形或半球形，并由介电弹性体材料构成。该方法包括围绕半环形插入器的表面定位多个导电元件，其从其最上端径向向内和向下延伸。该方法还包括安装所述至少一个部件，该部件包括安装在所述载体平面的相对侧上的至少一个半环形插入器。另外，该方法包括在所述电绝缘载体平面中形成至少一个贯通孔，以及在所述第一提到的至少一个半环形插入件与所述另外的至少一个反向半环形插入件之间形成电连接。

75. 发明授权

US08161248B2 Simplifying and speeding the management of intra-node cache coherence 失效
标题翻译：简化和加快节点内缓存一致性管理
公开(公告)号：US08161248B2
公开(公告)日：2012-04-17
申请号：US12953770
申请日：2010-11-24
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/167
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

76. 发明授权

US08122197B2 Managing coherence via put/get windows 失效
标题翻译：通过put / get窗口管理一致性
公开(公告)号：US08122197B2
公开(公告)日：2012-02-21
申请号：US12543890
申请日：2009-08-19
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

77. 发明授权

US08023358B2 System and method for providing a non-power-of-two burst length in a memory system 有权
标题翻译：在存储器系统中提供非二次突发长度的系统和方法
公开(公告)号：US08023358B2
公开(公告)日：2011-09-20
申请号：US12061045
申请日：2008-04-02
申请人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
发明人： Kyu-hyoun Kim , Paul W. Coteus , Warren E. Maule , Kenneth L. Wright
IPC分类号： G11C8/00
CPC分类号： G11C5/00 , G11C7/1018
摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.
摘要翻译：提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

78. 发明授权

US07952944B2 System for providing on-die termination of a control signal bus 有权
标题翻译：用于提供控制信号总线的管芯端接的系统
公开(公告)号：US07952944B2
公开(公告)日：2011-05-31
申请号：US12112391
申请日：2008-04-30
申请人： Kyu-hyoun Kim , Paul W. Coteus
发明人： Kyu-hyoun Kim , Paul W. Coteus
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/109 , H04L25/0298
摘要： A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.
摘要翻译：一种用于提供控制信号总线的管芯端接（ODT）的系统。该系统包括存储器件，其包括多个数据总线连接器，负载信号连接器和复位信号连接器中的一个或两个，控制总线连接器，ODT和机构。 ODT与控制总线连接器通信，ODT为连接到控制总线连接器的控制总线提供一定程度的终端电阻。该机构响应于经由一个或两个负载信号连接器和复位信号连接器接收到的信号，锁存经由数据总线连接器接收的数据。该数据用于设置由ODT提供的终端电阻的电平。

79. 发明申请

US20100279521A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
标题翻译：土地网阵列（LGA）利用金属激光器热电偶和其他多点接触几何
公开(公告)号：US20100279521A1
公开(公告)日：2010-11-04
申请号：US12061774
申请日：2008-04-03
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触。

80. 发明授权

US07658616B2 Groups of land grid interposers of different heights having metal-on elastomer hemi-torus shapes providing for electrical contact with at least one component on an opposite side of an electrically insulating carrier plate mounting interposers 失效
标题翻译：具有不同高度的地面栅格插入件组具有金属弹性体半环形状，其提供与电绝缘载板安装插入件的相对侧上的至少一个部件的电接触
公开(公告)号：US07658616B2
公开(公告)日：2010-02-09
申请号：US12328026
申请日：2008-12-04
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：包括电绝缘载体平面和不同高度的插入物分组的平面栅格阵列（LGA）插入器结构安装在所述载体平面的第一表面上。每个插入件在横截面中具有半环形结构并且由介电弹性体材料构成。多个导电元件围绕每个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触。

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