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71. 发明申请

US20120281323A1 INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION 有权
标题翻译：集成电路被动信号分配
公开(公告)号：US20120281323A1
公开(公告)日：2012-11-08
申请号：US13540500
申请日：2012-07-02
申请人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
发明人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
IPC分类号： H02H9/04
CPC分类号： H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。内部传输线路可以将信号被动地发送到内部传输线路的第二端。集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入线接收信号。第二位置可以不同于第一位置。还公开了其他实施例。

72. 发明授权

US08213894B2 Integrated circuit passive signal distribution 有权
标题翻译：集成电路无源信号分配
公开(公告)号：US08213894B2
公开(公告)日：2012-07-03
申请号：US11323370
申请日：2005-12-29
申请人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
发明人： Frank O'Mahony , Bryan Casper , James Jaussi , Matthew B. Haycock , Joseph Kennedy , Mozhgan Mansuri , Stephen R. Mooney
IPC分类号： H04B1/28
CPC分类号： H04L25/0278 , H03K5/15013 , H04L25/0292 , H04L25/0298
摘要： For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，集成电路可以包括集成电路的一个或多个层中的内部传输线。内部传输线可以被耦合以在内部传输线的第一端处接收来自外部传输线的信号，而不使用终端电路。内部传输线路可以将信号被动地发送到内部传输线路的第二端。集成电路还可以包括第一电路，其具有在内部传输线的第一位置处耦合到内部传输线的输入以接收信号，并且第二电路具有在内部传输的第二位置处耦合到内部传输线的输入线接收信号。第二位置可以不同于第一位置。还公开了其他实施例。

73. 发明授权

US06639426B2 Apparatus for testing simultaneous bi-directional I/O circuits 失效
标题翻译：用于测试同时双向I / O电路的装置
公开(公告)号：US06639426B2
公开(公告)日：2003-10-28
申请号：US10046448
申请日：2001-10-29
申请人： Matthew B. Haycock , Stephen R. Mooney
发明人： Matthew B. Haycock , Stephen R. Mooney
IPC分类号： H03K1900
CPC分类号： H04L1/243
摘要： A simultaneous bi-directional I/O circuit includes a first MUX in the reference select circuitry and a second, matching MUX in the pre-driver stage of the output buffer. In normal mode, the first MUX passes the driven data output signal, which controls the threshold of the differential receiver circuit between two different non-zero voltage levels, so that the receiver circuit can properly decode an incoming signal at the I/O node or pin. In an AC switching state or loopback test mode, the first MUX de-selects the driven data output signal from controlling the receiver circuit. This allows the receiver circuit to decode outgoing data that is being looped back as incoming data. The second MUX enables the reference select circuitry to switch at a rate that matches the output slew rate in order to provide high-speed operation. Also described are an electronic system, a data processing system, and various methods of testing simultaneous bi-directional I/O circuits.
摘要翻译：同时双向I / O电路包括参考选择电路中的第一MUX和输出缓冲器的前驱动器级中的第二匹配MUX。在正常模式下，第一MUX通过驱动数据输出信号，该信号控制差分接收器电路的阈值在两个不同的非零电压电平之间，使得接收机电路可以正确地解码I / O节点处的输入信号，销。在交流切换状态或环回测试模式中，第一MUX从控制接收机电路中取消驱动数据输出信号的选择。这允许接收器电路将作为输入数据循环的输出数据进行解码。第二MUX使参考选择电路以与输出转换速率匹配的速率切换，以便提供高速操作。还描述了电子系统，数据处理系统和测试同时双向I / O电路的各种方法。

74. 发明授权

US06420912B1 Voltage to current converter 有权
标题翻译：电压到电流转换器
公开(公告)号：US06420912B1
公开(公告)日：2002-07-16
申请号：US09735858
申请日：2000-12-13
申请人： Michael Pang-Cheng Hsu , Rajendran Nair , Stephen R. Mooney
发明人： Michael Pang-Cheng Hsu , Rajendran Nair , Stephen R. Mooney
IPC分类号： H02M1100
CPC分类号： H03F3/45219 , H03D13/003 , H03F3/45183 , H03F2203/45318 , H03F2203/45394 , H03F2203/45674 , H03L7/091
摘要： A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.
摘要翻译：电压 - 电流电路使用NMOS输入电压 - 电流（V-I）转换器和PMOS输入V-I转换器，同时驱动公共栅极输出级。每个V-I转换器包括跨导放大器和电流镜。公共栅极输出级包括两个串联的互补晶体管对。一对互补对驱动输出，另一个互补对偏置第一个。 V-I电路可以用作相位检测器的一部分，相位检测器又可以用作锁相环或延迟锁定环路的一部分。

75. 发明授权

US06351191B1 Differential delay cell with common delay control and power supply 失效
标题翻译：具有通用延迟控制和电源的差分延迟单元
公开(公告)号：US06351191B1
公开(公告)日：2002-02-26
申请号：US09584565
申请日：2000-05-31
申请人： Rajendran Nair , Stephen R. Mooney
发明人： Rajendran Nair , Stephen R. Mooney
IPC分类号： H03B524
CPC分类号： H03B5/24 , H03K3/011 , H03K3/0231 , H03K5/133 , H03K2005/00032 , H03K2005/00208 , H03L7/0995
摘要： A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that when the power supply voltage changes, the delay in the differential delay cell changes. The resistance presented by the load transistors changes as a function of the power supply voltage, as does the current sourced by the variable current source. The combination of changing resistance and changing current as the power supply voltage changes results in a substantially constant output voltage swing. A ring of differential delay cells is included in a voltage controlled oscillator, which is in turn included in a phase lock loop. The phase lock loop has a wide loop bandwidth and the voltage controlled oscillator has a good power supply rejection ratio.
摘要翻译：差分延迟单元包括负载晶体管和线性偏置的电流源晶体管。差分延迟单元的延迟控制输入也是电源输入，使得当电源电压变化时，差分延迟单元中的延迟变化。由负载晶体管提供的电阻随着电源电压的变化而变化，与可变电流源的电流一样。随着电源电压变化，电阻变化和电流变化的组合导致基本恒定的输出电压摆幅。差分延迟单元的环包括在压控振荡器中，其又包括在锁相环中。锁相环具有宽环路带宽，压控振荡器具有良好的电源抑制比。

76. 发明授权

US07031221B2 Fixed phase clock and strobe signals in daisy chained chips 失效
标题翻译：在菊花链芯片中固定相位时钟和选通信号
公开(公告)号：US07031221B2
公开(公告)日：2006-04-18
申请号：US10749677
申请日：2003-12-30
申请人： Stephen R. Mooney , Joseph T. Kennedy
发明人： Stephen R. Mooney , Joseph T. Kennedy
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1066 , G11C7/10 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C7/1093
摘要： In some embodiments, a chip includes first and second ports to provide first and second received data signals and first and second received strobe signal, respectively. An internal clock signal has a fixed phase relationship to the first received strobe signal and the second received strobe signal has an arbitrary phase relationship with the internal clock signal. First and second write blocks latch the first and second received data signals synchronously with the first and second received strobe signals, respectively. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括分别提供第一和第二接收数据信号的第一和第二端口以及第一和第二接收选通信号。内部时钟信号与第一接收选通信号具有固定的相位关系，第二接收选通信号与内部时钟信号具有任意的相位关系。第一和第二写入块分别与第一和第二接收选通信号同步地锁存第一和第二接收数据信号。描述和要求保护其他实施例。

77. 发明授权

US06453422B1 Reference voltage distribution for multiload i/o systems 有权
标题翻译：多负载i / o系统的参考电压分布
公开(公告)号：US06453422B1
公开(公告)日：2002-09-17
申请号：US09470686
申请日：1999-12-23
申请人： Sanjay Dabral , Stephen R. Mooney , T. Zale Schoenborn , Sam E. Calvin , Tim Frodsham
发明人： Sanjay Dabral , Stephen R. Mooney , T. Zale Schoenborn , Sam E. Calvin , Tim Frodsham
IPC分类号： G06F126
CPC分类号： H04L12/40032 , H04L12/4013
摘要： According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.
摘要翻译：根据本发明的实施例，要耦合到参考电压线的电路。电路包括噪声耦合电路，其基于驱动器是否驱动数据线，将来自电路的噪声耦合到参考电压线。

78. 发明授权

US06424175B1 Biased control loop circuit for setting impedance of output driver 有权
标题翻译：用于设置输出驱动器阻抗的偏置控制回路电路
公开(公告)号：US06424175B1
公开(公告)日：2002-07-23
申请号：US09659499
申请日：2000-09-11
申请人： Sriram R. Vangal , Matthew B. Haycock , Stephen R. Mooney
发明人： Sriram R. Vangal , Matthew B. Haycock , Stephen R. Mooney
IPC分类号： H03K1716
CPC分类号： H03K19/00384
摘要： A biased control loop for setting the impedance of an output driver includes a dummy driver having a variable output impedance, a sample and compare circuit to compare the output impedance of dummy output driver to a reference, and an up/down counter to modify the impedance. When the loop is locked, an error signal alternates positive and negative about a reference value. A digital filter produces a filtered version of the error signal with an apparent error value that does not alternate. The digital filter has a biased lock circuit that guarantees that the apparent error does not alternate. A simultaneous bidirectional port includes an output driver and the biased control loop to set the output driver impedance. When the output driver drives a bidirectional line and serves as a termination impedance for another driver, the reduced apparent error variation provides improved impedance matching.
摘要翻译：用于设置输出驱动器的阻抗的偏置控制环路包括具有可变输出阻抗的虚拟驱动器，用于将虚拟输出驱动器的输出阻抗与参考值进行比较的采样和比较电路以及用于修改阻抗的上/下计数器。当环路被锁定时，错误信号会围绕参考值交替正负。数字滤波器产生误差信号的滤波版本，具有不交替的明显误差值。数字滤波器具有偏置的锁定电路，保证视在误差不会交替。同时双向端口包括输出驱动器和偏置控制环路以设置输出驱动器阻抗。当输出驱动器驱动双向线并用作另一个驱动器的终端阻抗时，减小的视差误差提供改进的阻抗匹配。

79. 发明授权

US6087847A Impedance control circuit 失效
标题翻译：阻抗控制电路
公开(公告)号：US6087847A
公开(公告)日：2000-07-11
申请号：US902345
申请日：1997-07-29
申请人： Stephen R. Mooney , Matthew B. Haycock , Joseph T. Kennedy
发明人： Stephen R. Mooney , Matthew B. Haycock , Joseph T. Kennedy
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/003
CPC分类号： H03K19/017545 , H03K19/0005
摘要： Briefly, in accordance with one embodiment of the invention an integrated circuit includes: a digital feedback control circuit to adjust the impedance of an interface circuit output buffer based, at least in part, on having adjusted the impedance of a non-data signal output buffer coupled to an external impedance. Briefly, in accordance with another embodiment of the invention, a method of digitally adjusting the impedance of an interface circuit output buffer comprises: digitally adjusting the impedance of a non-data signal output buffer coupled to an external impedance, and digitally adjusting the impedance of the interface circuit output buffer based, at least in part, on the digitally adjusted impedance of the non-data signal output buffer.
摘要翻译：简而言之，根据本发明的一个实施例，集成电路包括：数字反馈控制电路，用于至少部分地基于调整了非数据信号输出缓冲器的阻抗来调整接口电路输出缓冲器的阻抗耦合到外部阻抗。简而言之，根据本发明的另一个实施例，一种数字调节接口电路输出缓冲器的阻抗的方法包括：数字调节耦合到外部阻抗的非数据信号输出缓冲器的阻抗，并数字调节阻抗所述接口电路输出缓冲器至少部分地基于非数据信号输出缓冲器的数字调节阻抗。

80. 发明授权

US06452428B1 Slew rate control circuit 有权
公开(公告)号：US06452428B1
公开(公告)日：2002-09-17
申请号：US09448048
申请日：1999-11-23
申请人： Stephen R. Mooney , Joseph T. Kennedy , Chaiyuth Chansungsan , Prantik K. Nag
发明人： Stephen R. Mooney , Joseph T. Kennedy , Chaiyuth Chansungsan , Prantik K. Nag
IPC分类号： H03K1716
CPC分类号： H04L25/0292 , H03K17/164 , H04L5/1423 , H04L25/0278 , H04L25/028
摘要： A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

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