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71. 发明授权

US07329939B2 Metal-insulator-metal capacitor and method of fabricating same 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US07329939B2
公开(公告)日：2008-02-12
申请号：US11205719
申请日：2005-08-17
申请人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
发明人： Louis L. Hsu , Rajiv V. Joshi , Chun-Yung Sung
IPC分类号： H01L29/92
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

72. 发明授权

US07291539B2 Amorphization/templated recrystallization method for hybrid orientation substrates 失效
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US07291539B2
公开(公告)日：2007-11-06
申请号：US11142646
申请日：2005-06-01
申请人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Edward Fogel , Katherine L. Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

73. 发明申请

US20070249131A1 Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权
标题翻译：用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法
公开(公告)号：US20070249131A1
公开(公告)日：2007-10-25
申请号：US11408522
申请日：2006-04-21
申请人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
发明人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译：用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害金属门。另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

74. 发明申请

US20070173003A1 Methods of manufacturing semiconductor devices with rotated substrates 有权
标题翻译：制造具有旋转衬底的半导体器件的方法
公开(公告)号：US20070173003A1
公开(公告)日：2007-07-26
申请号：US11710382
申请日：2007-02-23
申请人： Matthias Hierlemann , Chun-Yung Sung , Brian Greene , Manfred Eller
发明人： Matthias Hierlemann , Chun-Yung Sung , Brian Greene , Manfred Eller
IPC分类号： H01L21/337
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/78
摘要： Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
摘要翻译：集成电路在基板上以与基板的优选晶面方向（例如解理面）平行或垂直的方向旋转5至40度的角度定向在基板上。诸如晶体管的应力和迁移率的参数可以通过调节衬底的旋转角来优化。对于旋转的衬底CMOS器件设计，可以使用其他应力控制措施，例如应力控制或拉伸衬垫，通过NMOS晶体管，PMOS晶体管或两者，以进一步调节应力并提高性能。

75. 发明授权

US07247547B2 Method of fabricating a field effect transistor having improved junctions 失效
标题翻译：制造具有改善结的场效晶体管的方法
公开(公告)号：US07247547B2
公开(公告)日：2007-07-24
申请号：US10905454
申请日：2005-01-05
申请人： Huilong Zhu , Oleg Gluschenkov , Chun-Yung Sung
发明人： Huilong Zhu , Oleg Gluschenkov , Chun-Yung Sung
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/26506 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.
摘要翻译：提供一种形成场效应晶体管的方法，其包括从单晶半导体区域形成具有第一深度的非晶化半导体区域，随后在非晶化半导体区域的沟道部分的上方形成第一栅极导体。然后将包括n型掺杂剂和p型掺杂剂中的至少一种的第一掺杂剂注入第二深度到不被第一栅极导体掩蔽的非晶化半导体区域的部分，以形成与沟道相邻的源极/漏极部分一部分。然后将衬底加热以使非晶化半导体区域的沟道部分和源极/漏极部分重结晶。在加热步骤之后，至少部分重结晶的半导体区域被局部加热以在沟道部分和源极/漏极部分中的至少一个中激活掺杂剂。

76. 发明申请

US20050042835A1 Metal-insulator-metal capacitor and method of fabricating same 失效
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US20050042835A1
公开(公告)日：2005-02-24
申请号：US10643307
申请日：2003-08-19
申请人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
发明人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L21/20 , H01L21/8242
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

77. 发明授权

US06680542B1 Damascene structure having a metal-oxide-metal capacitor associated therewith 有权
标题翻译：具有与其相关联的金属氧化物 - 金属电容器的镶嵌结构
公开(公告)号：US06680542B1
公开(公告)日：2004-01-20
申请号：US09575214
申请日：2000-05-18
申请人： Gerald W. Gibson , Richard W. Gregor , Chun-Yung Sung , Daniel J. Vitkavage , Allen Yen
发明人： Gerald W. Gibson , Richard W. Gregor , Chun-Yung Sung , Daniel J. Vitkavage , Allen Yen
IPC分类号： H01L2348
CPC分类号： H01L28/40 , H01L23/5223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.
摘要翻译：本发明提供一种包括互连和电容器的半导体器件及其制造方法。该方法包括通过层间电介质层和位于层间电介质下面的电介质蚀刻停止层形成镶嵌互连结构，其中镶嵌互连结构接触第一互连结构。该方法还包括通过层间电介质层形成金属氧化物金属（MOM）电容器镶嵌结构，并终止在介电蚀刻停止层上。在替代实施例中，镶嵌结构可以是双镶嵌结构。此外，在另一个实施例中，镶嵌互连结构和MOM电容器可以构成较大集成电路的一部分。

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