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71. 发明申请

US20120119681A1 LIGHT DEVICES AND SYSTEMS 审中-公开
标题翻译：光设备和系统
公开(公告)号：US20120119681A1
公开(公告)日：2012-05-17
申请号：US12946682
申请日：2010-11-15
申请人： Ken Seidl , Edward Nowak , Paul Li
发明人： Ken Seidl , Edward Nowak , Paul Li
IPC分类号： H05B37/00
CPC分类号： H05B37/0272
摘要： The present invention provides switches and sensors that automatically turn on and/or off an associated device. In particular, the present invention provides lighting devices containing switches and sensors associated with the device that power/depower the device and systems and objects containing the device.
摘要翻译：本发明提供了自动打开和/或关闭相关设备的开关和传感器。特别地，本发明提供了包含与该装置相关联的开关和传感器的照明装置，其对设备和包含该装置的系统和对象进行功率/耗尽。

72. 发明申请

US20080042205A1 LOW-COST HIGH-PERFORMANCE PLANAR BACK-GATE CMOS 有权
标题翻译：低成本高性能平面背栅CMOS
公开(公告)号：US20080042205A1
公开(公告)日：2008-02-21
申请号：US11877865
申请日：2007-10-24
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/743 , H01L21/84 , H01L29/665 , H01L29/66553 , H01L29/66621 , H01L29/6675 , H01L29/78636 , H01L29/78648 , Y10S438/914
摘要： A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.
摘要翻译：提供了一种使用不太长或昂贵的处理步骤来制造具有优异的短沟道特性和减小电容的高性能平面背栅CMOS结构的方法。还提供了利用本发明的方法形成的高性能平面背栅CMOS结构。该方法包括在基板的上表面形成开口。此后，通过开口在衬底中形成掺杂剂区域。根据本发明的方法，掺杂剂区域限定本发明结构的背栅导体。接下来，在开口内形成具有至少一部分的前门导体。

73. 发明申请

US20070293031A1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 有权
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：US20070293031A1
公开(公告)日：2007-12-20
申请号：US11847384
申请日：2007-08-30
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

74. 发明申请

US20070290250A1 MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 审中-公开
标题翻译：多电介质FinFET结构与方法
公开(公告)号：US20070290250A1
公开(公告)日：2007-12-20
申请号：US11845972
申请日：2007-08-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译：公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。包括与栅极电介质不同的材料的盖可以位于鳍片上方。

75. 发明申请

US20070232020A1 HYBRID-ORIENTATION TECHNOLOGY BURIED N-WELL DESIGN 失效
标题翻译：混合技术渗透N型设计
公开(公告)号：US20070232020A1
公开(公告)日：2007-10-04
申请号：US11760836
申请日：2007-06-11
申请人： Wilfried Haensch , Edward Nowak
发明人： Wilfried Haensch , Edward Nowak
IPC分类号： H01L21/311
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure is provided that includes a hybrid orientated substrate having at least two coplanar surfaces of different surface crystal orientations, wherein one of the coplanar surfaces has bulk-like semiconductor properties and the other coplanar surface has semiconductor-on-insulator (SOI) properties. In accordance with the present invention, the substrate includes a new well design that provides a large capacitance from a retrograde well region of the second conductivity type to the substrate thereby providing noise decoupling with a low number of well contacts. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：提供一种半导体结构，其包括具有不同表面晶取向的至少两个共面表面的混合取向基板，其中共面中的一个具有块状半导体特性，而另一共面具有绝缘体上半导体（SOI）性质。根据本发明，衬底包括新的阱设计，其从第二导电类型的逆向阱区域向衬底提供大的电容，由此提供具有少量阱接触的噪声解耦。本发明还提供一种制造这种半导体结构的方法。

76. 发明申请

US20070108536A1 QUASI SELF-ALIGNED SOURCE/DRAIN FinFET PROCESS 失效
标题翻译： QUASI自对准源/漏极FinFET工艺
公开(公告)号：US20070108536A1
公开(公告)日：2007-05-17
申请号：US11164215
申请日：2005-11-15
申请人： MeiKei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
发明人： MeiKei Ieong , Thomas Ludwig , Edward Nowak , Qiqing Ouyang
IPC分类号： H01L21/8244
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66818 , H01L29/785
摘要： A method of forming a semiconductor structure including a plurality of finFFET devices in which crossing masks are employed in providing a rectangular patterns to define relatively thin Fins along with a chemical oxide removal (COR) process is provided. The present method further includes a step of merging adjacent Fins by the use of a selective silicon-containing material. The present invention also relates to the resultant semiconductor structure that is formed utilizing the method of the present invention.
摘要翻译：提供了一种形成包括多个finFFET器件的半导体结构的方法，其中使用交叉掩模提供矩形图案以限定相对薄的金属丝以及化学氧化物去除（COR）工艺。本方法还包括通过使用选择性含硅材料来合并相邻的金属丝的步骤。本发明还涉及利用本发明的方法形成的所得半导体结构。

77. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

78. 发明申请

US20060244077A1 ASYMMETRIC FIELD EFFECT TRANSISTORS (FETs) 有权
标题翻译：非对称场效应晶体管（FET）
公开(公告)号：US20060244077A1
公开(公告)日：2006-11-02
申请号：US10908095
申请日：2005-04-27
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/7391 , H01L29/785 , H01L29/7856 , H01L29/78624
摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a semiconductor channel region, (b) a semiconductor source block in direct physical contact with the semiconductor channel region; (c) a source contact region in direct physical contact with the semiconductor source block, wherein the source contact region comprises a first electrically conducting material, and wherein the semiconductor source block physically isolates the source contact region from the semiconductor channel region, and (d) a drain contact region in direct physical contact with the semiconductor channel region, wherein the semiconductor channel region is disposed between the semiconductor source block and the drain contact region, and wherein the drain contact region comprises a second electrically conducting material; and (e) a gate stack in direct physical contact with the semiconductor channel region.
摘要翻译：半导体结构及其形成方法。该结构包括（a）半导体沟道区，（b）与半导体沟道区直接物理接触的半导体源块; （c）与半导体源极块直接物理接触的源极接触区域，其中源极接触区域包括第一导电材料，并且其中半导体源极块将源极接触区域与半导体沟道区域物理隔离，并且（d ）与所述半导体沟道区域直接物理接触的漏极接触区域，其中所述半导体沟道区域设置在所述半导体源极块和所述漏极接触区域之间，并且其中所述漏极接触区域包括第二导电材料; 和（e）与半导体沟道区直接物理接触的栅叠层。

79. 发明申请

US20050163824A1 Modified polymeric films 审中-公开
标题翻译：改性聚合物膜
公开(公告)号：US20050163824A1
公开(公告)日：2005-07-28
申请号：US10514514
申请日：2003-05-12
申请人： Victoria Ayers , Jason Teckoe , Edward Nowak
发明人： Victoria Ayers , Jason Teckoe , Edward Nowak
IPC分类号： A61K9/48 , C08J5/18 , C08K5/00 , C08K5/092 , C08L1/10 , C08L1/26 , C08L1/28 , A61K9/70 , A61K31/716
CPC分类号： C08J5/18 , A61K9/4816 , C08J2301/28 , C08K5/092 , C08L1/26 , C08L1/28 , C08L1/284
摘要： A hydroxypropyl methyl cellulose film comprises hydroxypropyl methyl cellulose plasticised with a plasticiser comprising an organic acid or a salt of an organic acid, preferably lactic acid, or an alcohol or salt of an alcohol. The film is safe for human consumption and finds use as a wall material of an ingestible delivery capsule, e.g. containing a dose of a pharmaceutical preparation.
摘要翻译：羟丙基甲基纤维素膜包括用包含有机酸或有机酸盐，优选乳酸或酒精或醇的增塑剂增塑的羟丙基甲基纤维素。该片对于人类消费是安全的，并且被用作可摄取递送胶囊的壁材料，例如，含有一定剂量的药物制剂。

80. 发明申请

US20050104139A1 Method of forming fet with T-shaped gate 有权
标题翻译：用T形门形成胎儿的方法
公开(公告)号：US20050104139A1
公开(公告)日：2005-05-19
申请号：US11005659
申请日：2004-12-07
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Edward Nowak
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Edward Nowak
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/26586 , H01L21/2807 , H01L21/28114 , H01L21/28123 , H01L29/1045 , H01L29/42376 , H01L29/4966 , H01L29/4991 , H01L29/7833
摘要： An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.
摘要翻译： FET具有T形门。 FET具有与T的底部自对准的晕圈扩散，并且与顶部自对准的延伸扩散。因此，光环与延伸植入物分离，这提供了显着的优点。 T形门的顶部和底部可以由两种不同材料的层形成，例如锗和硅。两层被图案化在一起。然后，底层的暴露边缘被选择性地化学反应，并且蚀刻掉反应产物以提供凹口。在另一个实施例中，栅极由单个栅极导体形成。金属沿着侧壁共形沉积，凹陷蚀刻以暴露侧壁的顶部，并且被加热以沿底部形成硅化物。蚀刻硅化物以提供凹口。

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