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71. 发明申请

US20080258180A1 CROSS-SECTION HOURGLASS SHAPED CHANNEL REGION FOR CHARGE CARRIER MOBILITY MODIFICATION 有权
标题翻译：交叉部分HOURGLASS形状的通道区域用于充电载波移动性修改
公开(公告)号：US20080258180A1
公开(公告)日：2008-10-23
申请号：US11306721
申请日：2006-01-09
申请人： Huajie Chen , Dureseti Chidambarrao , Judson R. Holt , Qiqing Ouyang , Siddhartha Panda
发明人： Huajie Chen , Dureseti Chidambarrao , Judson R. Holt , Qiqing Ouyang , Siddhartha Panda
IPC分类号： H01L29/78 , H01L29/04 , H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.
摘要翻译：半导体结构和制造半导体结构的方法包括具有横截面沙漏形沟道区域的半导体衬底。应力施加层位于沟道区附近。沙漏形状可以在通过应力施加层纵向压缩应力时提供通道区域内的增强的垂直拉伸应力。

72. 发明授权

US07439123B2 Low resistance contact semiconductor device structure 失效
标题翻译：低电阻触点半导体器件结构
公开(公告)号：US07439123B2
公开(公告)日：2008-10-21
申请号：US11263261
申请日：2005-10-31
申请人： Dureseti Chidambarrao , William K. Henson
发明人： Dureseti Chidambarrao , William K. Henson
IPC分类号： H01L21/00
CPC分类号： H01L21/28518 , H01L21/2254 , H01L21/2652 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： A method for making a semiconductor device structure includes producing a substrate having formed thereon a gate with spacers, respective source and drain regions adjacent to the gate and an; disposing a first metallic layer on the gate with spacers, and the source and drain regions, disposing a second metallic layer on the first metallic layer; doping the first metallic layer with a first dopant through a portion of the second metal layer disposed over the second gate with spacers; and then heating the intermediate structure to a temperature and for a time sufficient to form a silicide of the first metallic layer. This first layer is, for example, Ni while the second layer is, for example, TiN.
摘要翻译：制造半导体器件结构的方法包括制造其上形成有栅极的衬底的衬底，与栅极相邻的相应的源极和漏极区域; 在栅极上用间隔物和源区和漏区设置第一金属层，在第一金属层上设置第二金属层; 通过设置在第二栅极上的第二金属层的一部分用间隔物掺杂第一金属层与第一掺杂剂; 然后将中间结构加热到足以形成第一金属层的硅化物的温度和时间。该第一层例如为Ni，而第二层为例如TiN。

73. 发明授权

US07436029B2 High performance CMOS device structures and method of manufacture 有权
标题翻译：高性能CMOS器件结构及其制造方法
公开(公告)号：US07436029B2
公开(公告)日：2008-10-14
申请号：US11867271
申请日：2007-10-04
申请人： Bruce B. Doris , Dureseti Chidambarrao , Suk Hoon Ku
发明人： Bruce B. Doris , Dureseti Chidambarrao , Suk Hoon Ku
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823864 , H01L29/7843 , Y10S257/90 , Y10S438/938
摘要： A semiconductor device structure includes at least two field effect transistors formed on same substrate, the first field effect transistor includes a spacer having a first width, the second field effect transistor includes a compressive spacer having a second width, the first width being different than said second width. Preferably, the first width is narrower than the second width. A tensile stress dielectric film forms a barrier etch stop layer over the transistors.
摘要翻译：半导体器件结构包括形成在同一衬底上的至少两个场效应晶体管，第一场效应晶体管包括具有第一宽度的间隔物，第二场效应晶体管包括具有第二宽度的压缩间隔物，第一宽度不同于所述第一宽度第二宽度。优选地，第一宽度比第二宽度窄。拉伸应力介电膜在晶体管上形成阻挡蚀刻停止层。

74. 发明申请

US20080237634A1 CRYSTALLOGRAPHIC RECESS ETCH FOR EMBEDDED SEMICONDUCTOR REGION 审中-公开
标题翻译：嵌入式半导体区域的晶体记录蚀刻
公开(公告)号：US20080237634A1
公开(公告)日：2008-10-02
申请号：US11693792
申请日：2007-03-30
申请人： Thomas W. Dyer , Dureseti Chidambarrao
发明人： Thomas W. Dyer , Dureseti Chidambarrao
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823425 , H01L29/045 , H01L29/165 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： Source and drain regions of an FET are etched by a crystallographic anisotropic etch to form a cavity surrounded by crystallographic facets. The exposure of the sidewalls of shallow trench isolation (STI) is avoided or reduced compared to the prior art. The crystallographic anisotropic etch may be combined with an isotropic etch or a recess etch to create undercuts beneath gate spacers and/or a pegging line beneath a top surface of the STI. The at least one cavity is then filled with a lattice-mismatched embedded material so that stress is applied to the channel of the FET. The resulting structure has increased containment of the embedded semiconductor region by shallow trench isolation. A reduction in stress due to the unconstrained sidewall area and an increase in the junction current due to the recessing of the pegging line are eliminated or alleviated.
摘要翻译：通过晶体各向异性蚀刻来蚀刻FET的源极和漏极区域，以形成由晶面刻划的空腔。与现有技术相比，避免或减少浅沟槽隔离（STI）的侧壁的暴露。结晶学各向异性蚀刻可以与各向同性蚀刻或凹陷蚀刻结合，以在STI的顶表面下方的门间隔物和/或钉住线之下产生底切。然后用晶格失配的嵌入材料填充至少一个空腔，使得应力施加到FET的沟道。所得到的结构通过浅沟槽隔离增加了嵌入式半导体区域的容纳。消除或减轻由于无约束侧壁区域引起的应力的减小和由于夹紧线的凹陷引起的结电流的增加。

75. 发明申请

US20080164535A1 CURVED FINFETS 有权
标题翻译：弯曲的熔体
公开(公告)号：US20080164535A1
公开(公告)日：2008-07-10
申请号：US11621228
申请日：2007-01-09
申请人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
发明人： Dureseti Chidambarrao , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik , Jeffrey W. Sleight , Richard Q. Williams
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/0649 , H01L29/66795 , H01L29/7843
摘要： A method of forming a transistor patterns a semiconductor fin on a substrate, such that the fin extends from the substrate. Then, the method forms a gate conductor over a central portion of the fin, leaving end portions of the fin exposed. Next, the end portions of the fin are doped with at least one impurity to leave the central portion of the fin as a semiconductor and form the end portions of the fin as conductors. The end portions of the fin are undercut to disconnect the end portions of the fin from the substrate, such that the fin is connected to the substrate along a central portion and is disconnected from the substrate along the end portions and that the end portions are free to move and the central portion is not free to move. A straining layer is formed on a first side of the fin and the straining layer imparts physical pressure on the fin such that the end portions are permanently moved away from a straight-line orientation with the central portion after the forming of the straining layer. Thus, the undercutting in combination with the forming of the straining layer curves the fin such that, when viewed from a top of the substrate, the fin is bowed and has a curved shape.
摘要翻译：一种形成晶体管的方法在衬底上形成半导体鳍片，使得鳍片从衬底延伸。然后，该方法在鳍片的中心部分上形成栅极导体，使翅片的端部部分露出。接下来，翅片的端部掺杂有至少一种杂质，以使翅片的中心部分作为半导体，并将翅片的端部形成为导体。翅片的端部被底切以使翅片的端部与基板断开，使得翅片沿着中心部分连接到基板，并且沿着端部与基板断开，并且端部部分是自由的移动，中央部分不能自由移动。在翅片的第一侧上形成有应变层，并且应变层在翅片上施加物理压力，使得端部在紧固层形成之后永久地与中心部分的直线取向远离。因此，与形成应变层相结合的底切使翅片弯曲，使得当从基板的顶部观察时，翅片弯曲并具有弯曲形状。

76. 发明授权

US07337420B2 Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models 有权
标题翻译：基于布局的调制方法和紧凑模型中氮化物衬垫应力效应的优化
公开(公告)号：US07337420B2
公开(公告)日：2008-02-26
申请号：US11193711
申请日：2005-07-29
申请人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
发明人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L29/7843
摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).
摘要翻译：用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

77. 发明申请

US20080042174A1 FIELD EFFECT TRANSISTORS (FETS) WITH INVERTED SOURCE/DRAIN METALLIC CONTACTS, AND METHOD OF FABRICATING SAME 有权
标题翻译：具有反相源/漏电金属接触的场效应晶体管（FET）及其制造方法
公开(公告)号：US20080042174A1
公开(公告)日：2008-02-21
申请号：US11923075
申请日：2007-10-24
申请人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
发明人： Michael Belyansky , Dureseti Chidambarrao , Lawrence Clevenger , Kaushik Kumar , Carl Radens
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76804 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.
摘要翻译：本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

78. 发明申请

US20080020531A1 SEMICONDUCTOR DEVICES HAVING TORSIONAL STRESSES 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US20080020531A1
公开(公告)日：2008-01-24
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

79. 发明申请

US20070296044A1 DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS 有权
标题翻译：具有双层蚀刻层和改性硅酸盐层的装置及相关方法
公开(公告)号：US20070296044A1
公开(公告)日：2007-12-27
申请号：US11850968
申请日：2007-09-06
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层具有与未暴露于形成双重氮化硅衬里的硅化物层基本相似的厚度和电阻。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

80. 发明申请

US20070296001A1 MULTIPLE CONDUCTION STATE DEVICES HAVING DIFFERENTLY STRESSED LINERS 失效
标题翻译：具有不同应力衬层的多个导电状态器件
公开(公告)号：US20070296001A1
公开(公告)日：2007-12-27
申请号：US11425511
申请日：2006-06-21
申请人： Dureseti Chidambarrao , David M. Onsongo
发明人： Dureseti Chidambarrao , David M. Onsongo
IPC分类号： H01L29/768
CPC分类号： H01L29/7833 , H01L21/823412 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.
摘要翻译：提供了一种场效应晶体管（“FET”），其包括包括沟道区，第一源极 - 漏极区和第二源极 - 漏极区的有源半导体区。有源半导体区域的主表面被分成相互排斥的第一部分和第二部分。第一衬里将第一应力施加到主表面的第一部分，并且第二衬里将第二应力施加到主表面的第二部分。第一和第二应力分别选自高拉伸应力，高压缩应力和中性应力，第一应力与第二应力不同。衬垫可以帮助区分在一个操作条件下由FET的第一部分传导的第一工作电流和在不同工作条件下由FET的第二部分传导的第二工作电流。

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