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71. 发明授权

US08423841B1 Method and systems for memory testing and test data reporting during memory testing 有权
标题翻译：内存测试中的内存测试和测试数据报告的方法和系统
公开(公告)号：US08423841B1
公开(公告)日：2013-04-16
申请号：US13118739
申请日：2011-05-31
申请人： Winston Lee , Albert Wu , Chorng-Lii Liou
发明人： Winston Lee , Albert Wu , Chorng-Lii Liou
IPC分类号： G11C29/00
CPC分类号： G06F11/2094 , G11C29/00 , G11C29/12 , G11C29/12015 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/48 , G11C29/56 , G11C29/72 , G11C2029/1208 , G11C2029/5602
摘要： The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.
摘要翻译：本发明提供了一种用于提高存储器测试效率，提高存储器测试速度，检测在存储器工作频率下发生的存储器故障以及减少冗余修复分析报告的数据的方法和系统。存储器测试系统包括第一存储器测试器，以较高的存储器工作频率从存储器提取故障存储器位置信息，外部存储器测试器以较低的存储器测试器频率接收失败的存储器位置信息，以及第一存储器测试器与外部存储器测试仪。存储器测试方法使用存储器测试器频率处的数据选通来计时在较高存储器工作频率处获得的故障存储器位置信息。此外，本发明的方法仅向外部存储器测试器报告足够的信息，以确定可用冗余资源可修复的行，列和单位故障。本发明还提供了一种冗余资源分配系统，其使用不良位置列表和相关联的不良位置列表来根据预定的优先顺序对失败的存储器位置进行分类，并且根据优先顺序分配冗余资源来修复失效的存储器位置。

72. 发明授权

US07694440B1 Insole cushioning device with repelling magnetic field 失效
标题翻译：鞋垫缓冲装置具有排斥磁场
公开(公告)号：US07694440B1
公开(公告)日：2010-04-13
申请号：US11618901
申请日：2006-12-31
申请人： Albert Wu
发明人： Albert Wu
IPC分类号： A43B13/38 , A43B13/18
CPC分类号： A43B17/02 , A43B1/0054
摘要： A system is disclosed for an insole for use in an article of footwear. The insole includes a bottom cushion layer; a lower intermediate layer; a middle flexible layer; an upper intermediate layer; and an upper cushion layer. The layers are coupled together by either lamination or gluing. The lower intermediate layer and the upper intermediate layer are respectively embedded with a first array of magnet elements and a second array of magnet elements, such that the first array of magnet elements and the second array of magnet elements generate a repelling magnetic field that results in a repelling mechanical force that pulls the upper intermediate layer away from the lower intermediate layer. This invention is not affected by material fatigue due to prolonged pressure or temperature stress that is common in insoles for use in articles of footwear.
摘要翻译：公开了一种用于鞋类物品的鞋垫的系统。鞋垫包括底垫层; 下中间层; 中间柔性层; 上层中间层; 和上缓冲层。层通过层压或胶合而连接在一起。下部中间层和上部中间层分别嵌有磁体元件的第一阵列和第二磁体元件阵列，使得磁体元件的第一阵列和第二磁体元件阵列产生排斥磁场，导致排斥磁场排斥机械力，其将上中间层拉离下中间层。由于用于鞋类物品的鞋垫中常见的压力或温度应力的延长，本发明不受材料疲劳的影响。

73. 发明授权

US07359261B1 Memory repair system and method 有权
标题翻译：内存修复系统和方法
公开(公告)号：US07359261B1
公开(公告)日：2008-04-15
申请号：US11349460
申请日：2006-02-07
申请人： Albert Wu , Sehat Sutardja
发明人： Albert Wu , Sehat Sutardja
IPC分类号： G11C7/00
CPC分类号： G06F11/0793 , G06F11/073 , G11C29/789
摘要： An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the memory module and the memory repair database, detects defective memory locations in the memory module, locates redundant memory elements in the memory module, stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database, and outputs the information. The memory control module includes a plurality of electrical fuses. Storing the information includes electrically altering at least one of the plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.
摘要翻译： IC包括存储数据和代码中的至少一个的存储器模块。存储器修复数据库存储与缺陷存储器地址有关的数据。存储器控制模块与存储器模块和存储器修复数据库通信，检测存储器模块中的缺陷存储器位置，将冗余存储器元件定位在存储器模块中，存储将缺陷存储器位置的存储器地址与冗余存储器元件相关联的信息内存修复数据库，并输出信息。存储器控制模块包括多个电保险丝。存储信息包括电改变多个电保险丝中的至少一个。冗余存储器解码器模块接收信息并将存储器地址物理地映射到冗余存储器位置。

74. 发明申请

US20080006948A1 Stack die packages 有权
标题翻译：堆栈包装
公开(公告)号：US20080006948A1
公开(公告)日：2008-01-10
申请号：US11801317
申请日：2007-05-09
申请人： Albert Wu , Huahung Kao
发明人： Albert Wu , Huahung Kao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/32145 , H01L2224/45144 , H01L2224/48145 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73253 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/01079 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： Integrated circuit packages having corresponding methods comprise: a substrate comprising first electric contacts; a first wirebond integrated circuit die mechanically coupled to the substrate and comprising second electric contacts electrically coupled to the first electric contacts of the substrate by first electrically conductive wires; a flip-chip integrated circuit die comprising third electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die by electrically conductive bumps; and a second wirebond integrated circuit die mechanically coupled to the flip-chip integrated circuit die and comprising fourth electric contacts electrically coupled to the second electric contacts of the first wirebond integrated circuit die, or the first electric contacts of the substrate, or both, by second electrically conductive wires.
摘要翻译：具有相应方法的集成电路封装包括：基板，包括第一电触头; 机械耦合到所述衬底并且包括通过第一导电线电耦合到所述衬底的所述第一电触点的第二电触点的第一引线键合集成电路模; 一种倒装芯片集成电路芯片，包括通过导电凸块电耦合到第一引线键合集成电路芯片的第二电触头的第三电触头; 以及第二引线键合集成电路芯片，其机械耦合到所述倒装芯片集成电路管芯并且包括电耦合到所述第一引线键合集成电路管芯的所述第二电触头或所述衬底的所述第一电触点或两者的第四电触点，第二导电线。

75. 发明申请

US20070284741A1 BALL-LIMITING METALLURGIES, SOLDER BUMP COMPOSITIONS USED THEREWITH, PACKAGES ASSEMBLED THEREBY, AND METHODS OF ASSEMBLING SAME 有权
标题翻译：限流金属，使用的焊接组合物，组装的组件及其组装方法
公开(公告)号：US20070284741A1
公开(公告)日：2007-12-13
申请号：US11840269
申请日：2007-08-17
申请人： Fay Hua , Albert Wu , Kevin Jeng , Krishna Seshan
发明人： Fay Hua , Albert Wu , Kevin Jeng , Krishna Seshan
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L21/563 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/05027 , H01L2224/05572 , H01L2224/13099 , H01L2224/16225 , H01L2224/16507 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , Y10T29/49144 , Y10T29/49179 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows and other higher temperature processes.
摘要翻译：为电气设备提供了限流冶金（BLM）堆叠。 BLM堆叠抵抗锡朝向器件的金属化迁移。还提供了一种焊料系统，其包括与高Pb焊料配合的衬底上的共晶Pb焊料，并且能够承受更高的温度回流和其它更高温度的工艺。

76. 发明授权

US07288845B2 Fabrication of wire bond pads over underlying active devices, passive devices and/or dielectric layers in integrated circuits 有权
标题翻译：在集成电路中的底层有源器件，无源器件和/或介电层上制造引线接合焊盘
公开(公告)号：US07288845B2
公开(公告)日：2007-10-30
申请号：US10434524
申请日：2003-05-08
申请人： Sehat Sutardja , Albert Wu , Jin-Yuan Lee , Mou-Shiung Lin
发明人： Sehat Sutardja , Albert Wu , Jin-Yuan Lee , Mou-Shiung Lin
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48644 , H01L2224/85399 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/04953 , H01L2924/00
摘要： A wire connection structure for an integrated circuit (IC) die includes a semiconductor wafer with an active device and/or a passive device. One or more dielectric layers are arranged adjacent to the active and/or passive device. One or more metal interconnect layers are arranged adjacent to the active and/or passive device. A contact pad is arranged in an outermost metal interconnect layer. A passivation layer is arranged over the outermost metal interconnect layer and includes at least one passivation opening that exposes the contact pad. A bond pad is arranged over the passivation layer and the active and/or passive device and is connected to the contact pad through the passivation opening. Formation of the bond pad does not damage the active and/or passive device.
摘要翻译：用于集成电路（IC）管芯的导线连接结构包括具有有源器件和/或无源器件的半导体晶片。一个或多个电介质层被布置为与有源和/或无源器件相邻。一个或多个金属互连层布置成与有源和/或无源器件相邻。接触垫布置在最外侧金属互连层中。钝化层布置在最外金属互连层上方，并且包括暴露接触焊盘的至少一个钝化开口。焊接层布置在钝化层和有源和/或无源器件上方，并通过钝化开口连接到接触焊盘。接合焊盘的形成不会损坏有源和/或无源器件。

77. 发明申请

US20070004086A1 Ball-limiting metallurgies, solder bump compositions used therewith, packages assembled thereby, and methods of assembling same 有权
标题翻译：限球冶金，与其一起使用的焊料凸块组合物，由此组装的封装，及其组装方法
公开(公告)号：US20070004086A1
公开(公告)日：2007-01-04
申请号：US11173238
申请日：2005-06-30
申请人： Fay Hua , Albert Wu , Kevin Jeng , Krishna Seshan
发明人： Fay Hua , Albert Wu , Kevin Jeng , Krishna Seshan
IPC分类号： H01L21/00
CPC分类号： H01L24/16 , H01L21/563 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/05027 , H01L2224/05572 , H01L2224/13099 , H01L2224/16225 , H01L2224/16507 , H01L2224/32225 , H01L2224/73204 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , Y10T29/49144 , Y10T29/49179 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： A ball-limiting metallurgy (BLM) stack is provided for an electrical device. The BLM stack resists tin migration toward the metallization of the device. A solder system is also provided that includes a eutectic-Pb solder on a substrate that is mated to a high-Pb solder, and that withstands higher temperature reflows and other higher temperature processes.
摘要翻译：为电气设备提供了限流冶金（BLM）堆叠。 BLM堆叠抵抗锡朝向器件的金属化迁移。还提供了一种焊料系统，其包括与高Pb焊料配合的衬底上的共晶Pb焊料，并且能够承受更高的温度回流和其它更高温度的工艺。

78. 发明授权

US5453388A Method of making an EEPROM 失效
标题翻译：制造EEPROM的方法
公开(公告)号：US5453388A
公开(公告)日：1995-09-26
申请号：US132941
申请日：1993-10-07
申请人： Ling Chen , Tien-ler Lin , Albert Wu
发明人： Ling Chen , Tien-ler Lin , Albert Wu
IPC分类号： H01L21/336 , H01L27/115 , H01L29/788 , H01L21/266 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/7883 , H01L27/115
摘要： Disclosed is a flash EEPROM cell needing only a 5 volt external source using an on-chip voltage multiplier circuit to provide high voltages necessary to effect Fowler-Nordheim tunneling during both the program and erase modes. Properties of dielectric layers between a floating gate and a control gate and between the floating gate and a drain region differ to facilitate programming and erasing of the floating gate. Also disclosed is a method for producing a flash EEPROM cell by forming the insulative layer between a floating gate and a control gate to have a capacitance lower than the capacitance of the insulating layer between the floating gate and a drain region.
摘要翻译：公开了使用片上电压倍增器电路仅需要5伏外部源的闪速EEPROM单元，以提供在编程和擦除模式期间实现Fowler-Nordheim隧穿所需的高电压。浮置栅极和控制栅极之间以及浮置栅极和漏极区域之间的介电层的性质不同，以便于浮动栅极的编程和擦除。还公开了一种通过在浮动栅极和控制栅极之间形成绝缘层以使电容低于浮置栅极和漏极区域之间的绝缘层的电容的电容来产生快闪EEPROM单元的方法。

79. 发明授权

US07958413B1 Method and system for memory testing and test data reporting during memory testing 有权
标题翻译：内存测试中的内存测试和测试数据报告的方法和系统
公开(公告)号：US07958413B1
公开(公告)日：2011-06-07
申请号：US12766809
申请日：2010-04-23
申请人： Winston Lee , Albert Wu , Chorng-Lii Liou
发明人： Winston Lee , Albert Wu , Chorng-Lii Liou
IPC分类号： G11C29/00
CPC分类号： G06F11/2094 , G11C29/00 , G11C29/12 , G11C29/12015 , G11C29/14 , G11C29/16 , G11C29/44 , G11C29/4401 , G11C29/48 , G11C29/56 , G11C29/72 , G11C2029/1208 , G11C2029/5602
摘要： The present invention provides a method and system for improving memory testing efficiency, raising the speed of memory testing, detecting memory failures occurring at the memory operating frequency, and reducing data reported for redundancy repair analysis. The memory testing system includes a first memory tester extracting failed memory location information from the memory at a higher memory operating frequency, an external memory tester receiving failed memory location information at a lower memory tester frequency, and an interface between the first memory tester and the external memory tester. The memory testing method uses data strobes at the memory tester frequency to clock out failed memory location information obtained at the higher memory operating frequency. In addition, the inventive method reports only enough information to the external memory tester for it to determine row, column and single bit failures repairable with the available redundant resources. The present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory locations according to a predetermined priority sequence, and allocates redundant resources to repair the failed memory locations according to the priority sequence.
摘要翻译：本发明提供了一种用于提高存储器测试效率，提高存储器测试速度，检测在存储器工作频率下发生的存储器故障以及减少冗余修复分析报告的数据的方法和系统。存储器测试系统包括第一存储器测试器，以较高的存储器工作频率从存储器提取故障存储器位置信息，外部存储器测试器以较低的存储器测试器频率接收失败的存储器位置信息，以及第一存储器测试器与外部存储器测试仪。存储器测试方法使用存储器测试器频率处的数据选通来计时在较高存储器工作频率处获得的故障存储器位置信息。此外，本发明的方法仅向外部存储器测试器报告足够的信息，以确定可用冗余资源可修复的行，列和单位故障。本发明还提供了一种冗余资源分配系统，其使用不良位置列表和相关联的不良位置列表来根据预定的优先顺序对失败的存储器位置进行分类，并且根据优先顺序分配冗余资源来修复失效的存储器位置。

80. 发明申请

US20090212410A1 STACK DIE PACKAGES 有权
标题翻译：堆叠包装
公开(公告)号：US20090212410A1
公开(公告)日：2009-08-27
申请号：US12434264
申请日：2009-05-01
申请人： Albert Wu , Huahung Kao
发明人： Albert Wu , Huahung Kao
IPC分类号： H01L25/065 , H01L23/52
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/32145 , H01L2224/45144 , H01L2224/48145 , H01L2224/48227 , H01L2224/731 , H01L2224/73207 , H01L2224/73253 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2924/01079 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact.
摘要翻译：集成电路封装包括包括第一触点的基板。机械地附接到基板的第一集成电路。所述第一集成电路包括第二接触。布置在第一集成电路上的第一再分配层。第一再分配层包括耦合到第二接触的迹线。第一线将第一触点连接到第二触点。倒装芯片集成电路包括通过导电凸块连接到迹线的第三触点。机械耦合到倒装芯片集成电路的第二集成电路。第二集成电路包括第四触点。第二线将第四触点连接到至少第二触点或第一触点。

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