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71. 发明申请

US20090008678A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090008678A1
公开(公告)日：2009-01-08
申请号：US12279010
申请日：2007-01-29
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Tatsuo Nakayama , Takashi Inoue
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201
摘要： An electron supply layer (13) is a layer which forms a heterojunction with a channel layer (12) and contains InzAlxGa1-zxN (0≦z
摘要翻译：电子供给层（13）是与沟道层（12）形成异质结并含有In z Al x Ga 1-z x N（0 <= z <1,0 x1 / 2 <= xa <？in-line-formula description =“In-line Formulas”end =“lead”？> x1 <= 0.3。<？in-line-formula description =“In-line Formulas”end = 尾巴“？>

72. 发明申请

US20080179743A1 Electrode, method for producing same and semiconductor device using same 有权
标题翻译：电极及其制造方法以及使用该电极的半导体装置
公开(公告)号：US20080179743A1
公开(公告)日：2008-07-31
申请号：US12007218
申请日：2008-01-08
申请人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Takashi Inoue , Yasuhiro Okamoto , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Hironobu Miyamoto , Yuji Ando , Takashi Inoue , Yasuhiro Okamoto , Masaaki Kuzuhara
IPC分类号： H01L29/45 , H01L21/283
CPC分类号： H01L29/452 , H01L21/28 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： There is provided a technology for obtaining an electrode having a low contact resistance and less surface roughness. There is provided an electrode comprising a semiconductor film 101, and a first metal layer 102 and a second metal layer 103 sequentially stacked in this order on the semiconductor film 101, characterized in that the first metal film 102 is formed of Al, and the second metal film 103 is formed of at least one metal selected from the group consisting of Nb, W, Fe, Hf, Re, Ta and Zr.
摘要翻译：提供了一种获得具有低接触电阻和较小表面粗糙度的电极的技术。提供了一种电极，其包括半导体膜101，以及顺序地依次层叠在半导体膜101上的第一金属层102和第二金属层103，其特征在于，第一金属膜102由Al形成，第二金属层103 金属膜103由选自Nb，W，Fe，Hf，Re，Ta和Zr中的至少一种金属形成。

73. 发明授权

US07071526B2 Semiconductor device having Schottky junction electrode 失效
标题翻译：具有肖特基结电极的半导体器件
公开(公告)号：US07071526B2
公开(公告)日：2006-07-04
申请号：US10518602
申请日：2003-06-17
申请人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
发明人： Yuji Ando , Hironobu Miyamoto , Yasuhiro Okamoto , Kensuke Kasahara , Tatsuo Nakayama , Masaaki Kuzuhara
IPC分类号： H01L27/095 , H01L29/47
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/475 , H01L29/7781 , H01L29/812
摘要： A GaN semiconductor device with improved heat resistance of the Schottky junction electrode and excellent power performance and reliability is provided. In this semiconductor device having a Schottky gate electrode 17 which is in contact with an AlGaN electron supplying layer 14, a gate electrode 17 comprises a laminated structure wherein a first metal layer 171 formed of any of Ni, Pt and Pd, a second metal layer 172 formed of any of Mo, Pt, W, Ti, Ta, MoSi, PtSi, WSi, TiSi, TaSi, MoN, WN, TiN and TaN, and a third metal layer formed of any of Au, Cu, Al and Pt. Since the second metal layer comprises a metal material having a high melting point, it works as a barrier to the interdiffusion between the first metal layer and the third metal layer, and the deterioration of the gate characteristics caused by high temperature operation is suppressed. Since the first metal layer contacting the AlGaN electron supplying layer 14 has a high work function, the Schottky barrier is high, and superior Schottky contact is obtained.
摘要翻译：提供了具有肖特基接合电极的耐热性改善并且具有优异的功率性能和可靠性的GaN半导体器件。在具有与AlGaN电子供给层14接触的肖特基栅电极17的该半导体器件中，栅电极17包括层叠结构，其中由Ni，Pt和Pd中的任一种形成的第一金属层171，第二金属层由Mo，Pt，W，Ti，Ta，MoSi，PtSi，WSi，TiSi，TaSi，MoN，WN，TiN和TaN中的任一种形成的第一金属层，以及由Au，Cu，Al和Pt中的任一种形成的第三金属层。由于第二金属层包括具有高熔点的金属材料，所以它作为第一金属层和第三金属层之间的相互扩散的障碍，并且抑制了由高温操作引起的栅极特性的劣化。由于与AlGaN电子供给层14接触的第一金属层具有高功函数，所以肖特基势垒高，得到优异的肖特基接触。

74. 发明申请

US20060054929A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060054929A1
公开(公告)日：2006-03-16
申请号：US10515886
申请日：2004-11-29
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kensuke Kasahara , Yasuhiro Okamoto , Masaaki Kuzuhara
IPC分类号： H01L31/109
CPC分类号： H01L29/7783 , H01L29/2003
摘要： A semiconductor device includes, on a substrate (101), a buffer layer (102), and an channel layer (104), consisting essentially of semiconductor of a wultzite compound of group III-V, having a (0001) plane as a principal plane. The channel layer is subjected to compressive strain. A carrier supplying layer (103) is interposed between the channel layer (104) and the buffer layer (102). The carrier supplying layer (103) consists essentially of semiconductor of a wultzite compound of group III-V as a main component. N-type impurities are doped into the entire or part of the carrier supplying layer (103).
摘要翻译：半导体器件在衬底（101）上包括缓冲层（102）和沟道层（104），该沟道层（104）主要由具有（0001）面作为主体的III-V族的无丝绒化合物的半导体组成飞机通道层经受压应变。载体供给层（103）插入在沟道层（104）和缓冲层（102）之间。载体供给层（103）主要由作为主要成分的III-V族的无水锰矿化合物的半导体构成。 N型杂质被掺杂到载体供给层（103）的整个或部分中。

75. 发明授权

US06765241B2 Group III nitride semiconductor device of field effect transistor type having reduced parasitic capacitances 失效
标题翻译：具有降低的寄生电容的场效应晶体管类型的III族氮化物半导体器件
公开(公告)号：US06765241B2
公开(公告)日：2004-07-20
申请号：US10362883
申请日：2003-02-27
申请人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
发明人： Yasuo Ohno , Nobuyuki Hayama , Kensuke Kasahara , Tatsuo Nakayama , Hironobu Miyamoto , Yuji Takahashi , Yuji Ando , Kohji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L29812
CPC分类号： H01L29/8126 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L29/045 , H01L29/2003
摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.
摘要翻译：具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。

76. 发明授权

US06492669B2 Semiconductor device with schottky electrode having high schottky barrier 有权
标题翻译：肖特基电极具有高肖特基势垒的半导体器件
公开(公告)号：US06492669B2
公开(公告)日：2002-12-10
申请号：US09892567
申请日：2001-06-28
申请人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
发明人： Tatsuo Nakayama , Yuji Ando , Hironobu Miyamoto , Kazuaki Kunihiro , Yuji Takahashi , Kensuke Kasahara , Nobuyuki Hayama , Yasuo Ohno , Kouji Matsunaga , Masaaki Kuzuhara
IPC分类号： H01L2980
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/2003 , H01L29/475 , H01L29/7783
摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.
摘要翻译：在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。载体供应层由AlGaN组成并具有拉伸应变。肖特基层由InGaN组成并具有压应变。在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

77. 发明授权

US5608239A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US5608239A
公开(公告)日：1997-03-04
申请号：US357216
申请日：1994-12-13
申请人： Hironobu Miyamoto , Tatsuo Nakayama
发明人： Hironobu Miyamoto , Tatsuo Nakayama
IPC分类号： H01L29/812 , H01L21/338 , H01L29/778 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/7783
摘要： The present invention relates to a field effect transistor with high speed and excellent high frequency characteristics. A hetero junction field effect transistor, comprising a first semiconductor layer that contains In, a second semiconductor layer that contains In whose composition ratio is smaller than that of the first semiconductor layer, and a third semiconductor layer whose electron affinity is smaller than that of the first semiconductor layer, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are successively disposed in the order, and wherein the thickness of the second semiconductor layer is equal to or larger than the thickness of two monolayers thereof and less than 4 nm. A current of this field effect transistor flows in the first semiconductor layer 3 and the second semiconductor layer 4 of the transistor. When the thickness of the second semiconductor layer 4 is 4 nm or more, the ratio of electrons that exist in the first semiconductor layer 3 is 85% or less of the case that the thickness of the second semiconductor layer 4 is almost zero. Thus, when the thickness of the second semiconductor layer 4 is decreased to the thickness of two monolayers thereof, the ratio of electrons that exist in the first semiconductor layer 3 becomes nearly 100%. Consequently, the high frequency characteristics of the transistor are improved.
摘要翻译：本发明涉及具有高速度和优异的高频特性的场效应晶体管。一种异质结场效应晶体管，包括含有In的第一半导体层，包含其组成比小于第一半导体层的组成比的第二半导体层，以及第三半导体层，其电子亲和力小于第一半导体层，其中第一半导体层，第二半导体层和第三半导体层依次依次布置，并且其中第二半导体层的厚度等于或大于其两个单层的厚度和更小的厚度超过4nm。该场效应晶体管的电流在晶体管的第一半导体层3和第二半导体层4中流动。当第二半导体层4的厚度为4nm以上时，在第二半导体层4的厚度几乎为零的情况下，存在于第一半导体层3中的电子的比例为85％以下。因此，当第二半导体层4的厚度减小到其两个单层的厚度时，存在于第一半导体层3中的电子的比例接近100％。因此，提高了晶体管的高频特性。

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