专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US08154640B2 Sub-pixels, unit pixels, image sensors and methods of operating the same 有权
标题翻译：子像素，单位像素，图像传感器及其操作方法
公开(公告)号：US08154640B2
公开(公告)日：2012-04-10
申请号：US12230363
申请日：2008-08-28
申请人： Dae-kil Cha , Bok-ki Min , Young-gu Jin , Won-joo Kim , Seung-hoon Lee , Yoon-dong Park
发明人： Dae-kil Cha , Bok-ki Min , Young-gu Jin , Won-joo Kim , Seung-hoon Lee , Yoon-dong Park
IPC分类号： H04N3/14 , H04N5/335 , H01L31/062 , H01L31/113
CPC分类号： H01L27/14679 , H01L27/14609 , H04N5/335 , H04N5/3355
摘要： An image sensor includes a plurality of unit pixels arranged in an array. Each unit pixel includes a plurality of sub-pixels configured to be irradiated by light having the same wavelength. Each sub-pixel includes a plurality of floating body transistors. Each floating body transistor includes a source region, a drain region, a floating body region between the source region and the drain region, and a gate electrode formed on the floating body region.
摘要翻译：图像传感器包括排列成阵列的多个单位像素。每个单位像素包括被配置为被具有相同波长的光照射的多个子像素。每个子像素包括多个浮体晶体管。每个浮体晶体管包括源极区域，漏极区域，源极区域和漏极区域之间的浮体区域以及形成在浮动体区域上的栅极电极。

72. 发明授权

US07990794B2 Semiconductor apparatuses and methods of operating the same 失效
标题翻译：半导体装置及其操作方法
公开(公告)号：US07990794B2
公开(公告)日：2011-08-02
申请号：US12585536
申请日：2009-09-17
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee
IPC分类号： G11C7/06
CPC分类号： G11C11/404 , G11C2211/4016 , H01L29/7841
摘要： A method of operating a semiconductor device is provided including applying a constant source voltage to a source line.
摘要翻译：提供了一种操作半导体器件的方法，包括向源极线施加恒定的源极电压。

73. 发明授权

US07932551B2 Nonvolatile memory device and method of fabricating the same comprising a dual fin structure 失效
标题翻译：非易失性存储器件及其制造方法包括双鳍结构
公开(公告)号：US07932551B2
公开(公告)日：2011-04-26
申请号：US11902511
申请日：2007-09-21
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Sung-jae Byun
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/42336 , H01L29/66803
摘要： A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.
摘要翻译：提供非易失性存储器件。在非易失性存储器件中，第一导电类型的半导体衬底包括第一和第二鳍片。公共位线电极将第一鳍片的一端连接到第二鳍片的一端。控制栅电极覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。位于公共位线电极和控制栅电极之间的第一串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。位于第一串选择栅极电极和控制栅电极之间的第二串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。

74. 发明授权

US07894265B2 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US07894265B2
公开(公告)日：2011-02-22
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C5/06 , G11C16/04 , G11C16/10 , G11C16/26
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.
摘要翻译：非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

75. 发明授权

US07885115B2 Non-volatile memory devices and methods of operating non-volatile memory devices 有权
标题翻译：非易失性存储器件和操作非易失性存储器件的方法
公开(公告)号：US07885115B2
公开(公告)日：2011-02-08
申请号：US12318651
申请日：2009-01-05
申请人： Tae-hee Lee , Won-joo Kim , June-mo Koo , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , June-mo Koo , Tae-eung Yoon
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： A non-volatile memory device, which includes a plurality of memory transistors that are coupled with a plurality of bit lines and a plurality of word lines, and methods of operating a non-volatile memory device are provided. A selected bit line for programming and unselected bit lines for preventing programming are determined from the plurality of bit lines. An inhibiting voltage is applied to at least one inhibiting word line chosen from the plurality of word lines. The at least one inhibiting word line includes a word line positioned closest to a string selection line. A programming voltage is applied to a selected word line chosen from the plurality of word lines. Data is programmed into a memory transistor coupled with the selected word line and the selected bit line while preventing data from being programming into memory transistors coupled with the unselected bit line.
摘要翻译：提供了包括与多个位线和多个字线耦合的多个存储晶体管的非易失性存储器件以及操作非易失性存储器件的方法。从多个位线确定用于编程的选择位线和用于防止编程的未选位线。对从多个字线中选择的至少一个禁止字线施加抑制电压。至少一个禁止字线包括最靠近字符串选择线定位的字线。将编程电压施加到从多个字线中选择的选定字线。数据被编程到与所选择的字线和所选择的位线耦合的存储晶体管中，同时防止数据被编程到与未选位线耦合的存储晶体管中。

76. 发明授权

US07829932B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07829932B2
公开(公告)日：2010-11-09
申请号：US11980632
申请日：2007-10-31
申请人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun
发明人： Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Won-joo Kim , June-mo Koo , Kyoung-Iae Cho , Jae-woong Hyun , Sung-jae Byun
IPC分类号： H01L29/788
CPC分类号： H01L29/785 , H01L21/76897 , H01L29/41791 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/7851 , H01L29/7881 , H01L29/792 , H01L2029/7858
摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.
摘要翻译：示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。半导体器件包括半导体衬底，半导体柱和接触插塞。半导体衬底包括至少一对使用（或功能）作为活性区的翅片。半导体柱可以插入翅片的部分之间以连接散热片。接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。

77. 发明授权

US07750393B2 Non-volatile memory device with independent channel regions adjacent different sides of a common control gate 失效
标题翻译：具有与公共控制门不同侧相邻的独立通道区域的非易失性存储器件
公开(公告)号：US07750393B2
公开(公告)日：2010-07-06
申请号：US11987008
申请日：2007-11-26
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/7885 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.
摘要翻译：提供了非易失性存储器件的示例性实施例及其制造方法。非易失性存储器件可以包括布置在半导体衬底上的控制栅电极，介于半导体衬底和控制栅电极之间的栅极绝缘层，介于栅极绝缘层和控制栅电极之间的存储节点层，插入在所述存储节点层和所述控制栅电极之间的阻挡绝缘层，沿着所述控制栅电极的第一侧的第一掺杂剂掺杂区域和沿着所述控制栅电极的第二侧的第二掺杂剂掺杂区域。第一掺杂剂掺杂区域可以与第二掺杂剂掺杂区域交替。换句话说，每个第二掺杂剂掺杂区域可以被布置在与第一掺杂剂掺杂区域中的一个相邻的控制栅电极的第二侧上的区域中。

78. 发明申请

US20100097124A1 Method of operating semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US20100097124A1
公开(公告)日：2010-04-22
申请号：US12462176
申请日：2009-07-30
申请人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee , Dae-kil Cha
发明人： Sang-moo Choi , Won-joo Kim , Tae-hee Lee , Dae-kil Cha
IPC分类号： H03K3/01
CPC分类号： H01L27/10802 , G11C11/404 , G11C2207/2227 , G11C2211/4016 , H01L21/84 , H01L27/10844 , H01L29/7841
摘要： Provided is a method of operating a semiconductor device, wherein an operating mode is set by adjusting timing of a voltage pulse or by adjusting a voltage level of the voltage pulse.
摘要翻译：提供了一种操作半导体器件的方法，其中通过调整电压脉冲的定时或通过调节电压脉冲的电压电平来设置操作模式。

79. 发明申请

US20090285030A1 MULTI-BIT NONVOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权
标题翻译：多位非易失性存储器件及其操作方法
公开(公告)号：US20090285030A1
公开(公告)日：2009-11-19
申请号：US11335618
申请日：2006-01-20
申请人： Dong-Hun Kang , Jeong-Hee Han , Wan-Jun Park , Won-Joo Kim , Jae-Woong Hyun
发明人： Dong-Hun Kang , Jeong-Hee Han , Wan-Jun Park , Won-Joo Kim , Jae-Woong Hyun
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C13/025 , B82Y10/00 , G11C11/56 , G11C2213/17 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923 , H01L51/0048 , H01L51/0554 , Y10S977/938 , Y10S977/943
摘要： A memory device may include a channel including at least one carbon nanotube. A source and a drain may be arranged at opposing ends of the channel and may contact different parts of the channel. A first storage node may be formed under the channel, and a second storage node may be formed on the channel. A first gate electrode may be formed under the first storage node and a second gate electrode may be formed on the second storage node.
摘要翻译：存储器件可以包括包括至少一个碳纳米管的通道。源极和漏极可以布置在通道的相对端处并且可以接触通道的不同部分。可以在信道下形成第一存储节点，并且可以在信道上形成第二存储节点。第一栅电极可以形成在第一存储节点下方，并且第二栅电极可以形成在第二存储节点上。

80. 发明申请

US20090122613A1 Non-volatile memory device and method of operating the same 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20090122613A1
公开(公告)日：2009-05-14
申请号：US12149213
申请日：2008-04-29
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon , Tae-hee Lee
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/10 , G11C2213/71
摘要： A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection lines. The plurality of NAND strings may be on the plurality of semiconductor layers. Each of the plurality of NAND strings may include a plurality of memory cells and/or at least one string selection transistor arranged in a NAND-cell array. The common bit line may be commonly connected to each of the NAND strings at a first end of the memory cells. The common source line may be commonly connected to each of the NAND strings at a second end of the memory cells. The plurality of string selection lines may be coupled to the at least one string selection transistor included in each of the NAND strings such that a signal applied to the common bit line is selectively applied to the NAND strings.
摘要翻译：非易失性存储器件可以包括多个堆叠半导体层，多个NAND串，公共位线，公共源极线和/或多个串选择线。多个NAND串可以在多个半导体层上。多个NAND串中的每一个可以包括布置在NAND单元阵列中的多个存储单元和/或至少一个串选择晶体管。公共位线可以在存储器单元的第一端处共同连接到每个NAND串。公共源极线可以在存储器单元的第二端处共同连接到每个NAND串。多个串选择线可以耦合到包括在每个NAND串中的至少一个串选择晶体管，使得施加到公共位线的信号被选择性地施加到NAND串。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式