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71. 发明授权

US6101151A Synchronous semiconductor memory device employing temporary data output stop scheme 失效
标题翻译：采用临时数据输出停止方案的同步半导体存储器件
公开(公告)号：US6101151A
公开(公告)日：2000-08-08
申请号：US196245
申请日：1998-11-20
申请人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
发明人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
IPC分类号： G11C11/413 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1072
摘要： In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.
摘要翻译：在同步半导体存储器件中，来自内部定时时钟信号产生电路的内部时钟信号以树形式被驱动电路分支并且被施加到输出缓冲器和数据与内部时钟信号同步输出，第一级的电路由NAND门和反相器构成。当暂时停止输出时，使能信号被设置为“L”电平，使得与非门关闭，从而停止对每个驱动电路的时钟信号的输出，从而降低功耗。

72. 发明授权

US6091659A Synchronous semiconductor memory device with multi-bank configuration 失效
标题翻译：具有多组配置的同步半导体存储器件
公开(公告)号：US6091659A
公开(公告)日：2000-07-18
申请号：US318433
申请日：1999-05-25
申请人： Naoya Watanabe , Katsumi Dosaka
发明人： Naoya Watanabe , Katsumi Dosaka
IPC分类号： G11C11/407 , G11C7/10 , G11C8/16 , G11C11/401 , G11C11/409 , G11C8/00
CPC分类号： G11C8/16 , G11C7/1006
摘要： Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.
摘要翻译：提供用于共享读出放大器频带的存储器块，共同提供用于传送内部数据的存储器块的全局IO（GIOB）总线以及与存储器块相对应地提供的本地IO总线的连接控制是基于与列选择操作。彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。当共享耦合到另一个存储器块的读出放大器的存储器块被寻址时，另一个存储块被去激活，然后寻址存储器块被访问，当输出有效数据时，这样的有效数据输出由数据有效信号发出。

73. 发明授权

US5963502A Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing 失效
标题翻译：时钟同步型半导体存储器件能够以正确的时序输出读时钟信号
公开(公告)号：US5963502A
公开(公告)日：1999-10-05
申请号：US112439
申请日：1998-07-09
申请人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
发明人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , H03L7/06 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.
摘要翻译：作为包括在PLL电路中的压控振荡器，具有与循环不同的结构的电压控制延迟电路，该PLL电路又由外部时钟信号产生内部时钟信号，由PLL电路的控制电压控制，电压控制延迟电路的延迟输出由选择电路根据游标调节计数器的输出信号选择，以产生读时钟信号。因此，可以实现用于优化控制器中的数据输入定时的游标，其总是具有恒定的延迟量，而与操作环境的变化无关。

74. 发明授权

US5956349A Semiconductor memory device for high speed data communication capable of accurate testing of pass/fail and memory system employing the same 失效
标题翻译：用于高速数据通信的半导体存储器件，能够对通过/失败的精确测试以及采用该通道的存储器系统进行测试
公开(公告)号：US5956349A
公开(公告)日：1999-09-21
申请号：US781248
申请日：1997-01-10
申请人： Naoya Watanabe , Akira Yamazaki
发明人： Naoya Watanabe , Akira Yamazaki
IPC分类号： G06F11/08 , G06F12/06 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/12 , G11C29/14 , G11C29/44 , G11C29/48
CPC分类号： G11C29/48 , G11C29/14 , G11C29/44
摘要： A memory includes a built-in testing circuit for determining pass/fail of a memory portion and an identifier register for storing identification value for identifying the memory. The memory performs a testing operation according to a command provided from a controller via a send link and sends the result of that testing to a sync link. Thus, the memory controller can identify a defective memory cell. In this way, erroneous operation of the system due to a defective memory cell in a memory system can be prevented.
摘要翻译：存储器包括用于确定存储器部分的通过/失败的内置测试电路和用于存储用于识别存储器的识别值的标识符寄存器。存储器根据从控制器经由发送链路提供的命令执行测试操作，并将该测试的结果发送到同步链路。因此，存储器控制器可以识别有缺陷的存储器单元。以这种方式，可以防止由于存储器系统中的缺陷存储器单元导致的系统的错误操作。

75. 发明授权

US5689289A Image recording apparatus 失效
标题翻译：图像记录装置
公开(公告)号：US5689289A
公开(公告)日：1997-11-18
申请号：US348223
申请日：1994-11-28
申请人： Naoya Watanabe , Makoto Kobayashi , Junji Iguchi , Yasuyuki Shinada , Yukio Nohata , Yuji Shimahara
发明人： Naoya Watanabe , Makoto Kobayashi , Junji Iguchi , Yasuyuki Shinada , Yukio Nohata , Yuji Shimahara
IPC分类号： B41J2/175 , B41J11/46 , B41J29/393 , B41J2/195 , B41J2/205
CPC分类号： B41J29/393 , B41J11/46 , B41J2/17566
摘要： A standard print mode or a thinning print mode can be selected at will by an input from an operation panel to record image data received by a receiving means section in a selected print mode using an ink jet recording head, And after one page of image recording, a footer mark is recorded on the trailing portion of the recording paper, and sensed by a photo sensor to determine whether or not the ink is present. This footer mark is recorded in the standard print mode without regard to the selected print mode. Thereby, the false detection of the predetermined image recorded on the recording medium, after a predefined amount of image data has been recorded, can be prevented.
摘要翻译：可以通过来自操作面板的输入随意选择标准打印模式或间隔打印模式，以使用喷墨记录头在所选择的打印模式中记录由接收装置部分接收的图像数据，并且在一页图像记录之后在记录纸的尾部记录有脚印标记，并由光传感器感测，以确定是否存在墨。这种页脚标记以标准打印模式记录，而不考虑所选的打印模式。因此，可以防止在记录了预定量的图像数据之后记录在记录介质上的预定图像的错误检测。

76. 发明授权

US09400522B2 Multiple display portable terminal apparatus with position-based display modes 有权
标题翻译：具有位置显示模式的多显示便携式终端设备
公开(公告)号：US09400522B2
公开(公告)日：2016-07-26
申请号：US13457144
申请日：2012-04-26
申请人： Akiko Inami , Naoya Watanabe
发明人： Akiko Inami , Naoya Watanabe
IPC分类号： G09G5/00 , G06F1/16 , G06F3/14 , H04M1/02
CPC分类号： G06F1/1641 , G06F1/1616 , G06F1/1624 , G06F1/1677 , G06F3/1438 , G06F2200/1614 , G09G2354/00 , H04M1/0214 , H04M1/0235 , H04M1/0245 , H04M2250/12 , H04M2250/16
摘要： A portable terminal apparatus is provided, which includes a first cabinet having a first display surface, a second cabinet having a second display surface, a support mechanism which supports the first and second cabinets to be switchable between first and second arrangement states which are different in a relative position between the first and second display surfaces, and a control unit which controls a display mode of the first and second display surfaces according to the switching between the first and second arrangement states.
摘要翻译：提供了一种便携式终端设备，其包括具有第一显示表面的第一机柜，具有第二显示表面的第二机柜，支撑机构，其支撑第一和第二机柜，以在第一和第二布置状态之间切换，第一显示面和第二显示面之间的相对位置，以及根据第一和第二布置状态之间的切换来控制第一和第二显示面的显示模式的控制单元。

77. 发明授权

US08902624B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US08902624B2
公开(公告)日：2014-12-02
申请号：US12849384
申请日：2010-08-03
申请人： Naoya Watanabe
发明人： Naoya Watanabe
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.
摘要翻译：本发明提供一种能够比常规操作更高频率操作的内容可寻址存储器。当从搜索控制电路提供的搜索使能信号被断言时，每个搜索线驱动器经由搜索线对将搜索数据传送到CAM存储器阵列的每个CAM单元。搜索线使能信号通过耦合到搜索控制电路的单个控制信号线发送到搜索线驱动器。控制信号线以这样的方式耦合到搜索线驱动器，使得搜索线使能信号以搜索线驱动器的排列顺序从搜索线驱动器和控制信号线之间的耦合节点从远离的一侧从匹配放大器观看。

78. 发明授权

US08859279B2 Cell detachment method 有权
标题翻译：细胞分离法
公开(公告)号：US08859279B2
公开(公告)日：2014-10-14
申请号：US11810768
申请日：2007-06-07
申请人： Amiko Nihei , Masatsugu Shigeno , Yoshiharu Shirakawabe , Akira Inoue , Osamu Matsuzawa , Naoya Watanabe
发明人： Amiko Nihei , Masatsugu Shigeno , Yoshiharu Shirakawabe , Akira Inoue , Osamu Matsuzawa , Naoya Watanabe
IPC分类号： C12N5/00 , C12M1/00
CPC分类号： C12M47/04 , C12M33/00
摘要： A cell detachment method for detaching only a desired cell from a plurality of cells cultured on a substrate under predetermined culture environment conditions by using a scanning probe microscope having a probe, comprising: observing the plural cells; specifying the cell to be detached; moving the probe onto the specified cell; and pressing the prove against the specified cell with a predetermined force so as to detach the cell from the substrate.
摘要翻译：一种细胞分离方法，其通过使用具有探针的扫描探针显微镜，在预定的培养环境条件下从仅在基质上培养的多个细胞中仅去除所需细胞，包括：观察所述多个细胞; 指定要分离的单元格; 将探针移动到指定的细胞上; 并用预定的力将证明压在指定的电池上，以将电池与基板分离。

79. 发明授权

US07954471B2 Spark ignited internal combustion engine and manufacturing the same 有权
标题翻译：火花点火的内燃机和制造相同
公开(公告)号：US07954471B2
公开(公告)日：2011-06-07
申请号：US12497314
申请日：2009-07-02
申请人： Toshiaki Nishimoto , Naoya Watanabe , Kazuhiro Nagatsu , Masatoshi Hidaka , Hiroaki Abe
发明人： Toshiaki Nishimoto , Naoya Watanabe , Kazuhiro Nagatsu , Masatoshi Hidaka , Hiroaki Abe
IPC分类号： F02B19/00 , F02B5/00 , F02F3/26
CPC分类号： F02B23/104 , F02B2075/125 , F02F3/26 , Y02T10/123 , Y02T10/125
摘要： There is provided a spark ignited internal combustion engine having a geometric compression ratio of 13.0 or greater. The engine comprises combustion chambers having a cylinder stroke volume of 0.3 liter or greater, with the spark plug in the chamber ceiling having its spark point in the combustion chamber, and a cavity being formed on the top surface of the piston. At least part of the cavity defines a spherical surface that a hypothetical sphere having its center at the spark point contacts when the piston is at top dead center. The cavity is formed so that V2/V1≧0.31, where V1 is top-dead-center combustion chamber volume, and V2 is the volume of the part of the hypothetical sphere not interfering with the combustion chamber floor or ceiling at top dead center. The flame thus spreads with less interference, shortening combustion duration and reducing fuel consumption.
摘要翻译：提供几何压缩比为13.0以上的火花点火式内燃机。发动机包括具有0.3升或更大的气缸行程体积的燃烧室，其中室顶部中的火花塞在燃烧室中具有其火花点，并且在活塞的顶表面上形成空腔。空腔的至少一部分限定了球形表面，当活塞处于上止点时，具有其在火花点处的中心的假想球接触。空腔形成为V2 /V1≥0.31，其中V1是上死点燃烧室体积，V2是假想球体部分的体积，不会干扰上死点处的燃烧室地板或天花板。因此，火焰以较少的干扰扩散，缩短燃烧持续时间并降低燃料消耗。

80. 发明申请

US20110026288A1 CONTENT ADDRESSABLE MEMORY 有权
标题翻译：内容可寻址内存
公开(公告)号：US20110026288A1
公开(公告)日：2011-02-03
申请号：US12849384
申请日：2010-08-03
申请人： Naoya Watanabe
发明人： Naoya Watanabe
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/00
摘要： The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each CAM cell of a CAM memory array via a search line pair. The search line enable signal is transmitted to the search line drivers via a single control signal line coupled to the search control circuit. The control signal line is coupled to the search line drivers in such a manner that the search line enable signal passes through coupling nodes between the search line drivers and the control signal line in an arrangement order of the search line drivers from the side far away as viewed from match amplifiers.
摘要翻译：本发明提供一种能够比常规操作更高频率操作的内容可寻址存储器。当从搜索控制电路提供的搜索使能信号被断言时，每个搜索线驱动器经由搜索线对将搜索数据传送到CAM存储器阵列的每个CAM单元。搜索线使能信号通过耦合到搜索控制电路的单个控制信号线发送到搜索线驱动器。控制信号线以这样的方式耦合到搜索线驱动器，使得搜索线使能信号以搜索线驱动器的排列顺序从搜索线驱动器和控制信号线之间的耦合节点从远离的一侧从匹配放大器观看。

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