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71. 发明授权

US06576555B2 Method of making upper conductive line in dual damascene having lower copper lines 有权
标题翻译：在具有较低铜线的双镶嵌中制造上导线的方法
公开(公告)号：US06576555B2
公开(公告)日：2003-06-10
申请号：US09755850
申请日：2001-01-05
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21311
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76844 , H01L21/76883
摘要： A method of making upper conductive lines in dual damascene process having lower copper conductive lines is disclosed. The processes begin from a substrate having lower copper conductive lines and a via formed in the nitride layer. An oxide layer plays as IMD is then formed on the nitride layer. Next, the oxide layer is patterned to form trenches. Thereafter, a barrier layer is deposited on the resulting exposed surface. An anisotropic etching process is then carried out to form barrier spacers on the sidewall of the trenches. Subsequently, an inert gas bombardment is done to remove a copper oxide layer so as to clean a surface of the via. Next, a conductive layer refilled in the trenches followed by a CMP process is successively performed to form a plurality of upper conductive lines.
摘要翻译：公开了一种在具有较低铜导线的双镶嵌工艺中制造上导电线的方法。该工艺从具有较低铜导电线和在氮化物层中形成的通孔的衬底开始。随后在氮化物层上形成IMD，氧化物层起作用。接下来，对氧化物层进行图案化以形成沟槽。此后，在所得到的暴露表面上沉积阻挡层。然后进行各向异性蚀刻工艺以在沟槽的侧壁上形成阻挡间隔物。随后，进行惰性气体轰击以除去氧化铜层以清洁通孔的表面。接下来，依次执行在沟槽中再填充的导电层，然后进行CMP处理，以形成多个上导电线。

72. 发明授权

US06531781B2 Fabrication of transistor having elevated source-drain and metal silicide 有权
公开(公告)号：US06531781B2
公开(公告)日：2003-03-11
申请号：US09734893
申请日：2000-12-13
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2348
CPC分类号： H01L29/66583 , H01L21/28518 , H01L21/28525 , H01L29/41783 , H01L29/66545 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a transistor, the method comprises following steps: provides a substrate; covers part of the substrate by a doped amorphous silicon layer and covers part of the substrate by a first dielectric layer; forms a metal silicide layer on the doped amorphous silicon layer; removes the first dielectric layer to form a window; forms a second dielectric layer on both the metal silicide layer and the hole; and forms a conductor layer on the second dielectric layer. Significantly, during formation of the second dielectric layer, not only numerous dopants inside the doped amorphous silicon layer are driven into the substrate but also the doped amorphous silicon layer usually is re-crystallized to form an epi-like silicon layer.

73. 发明授权

US06528402B2 Dual salicidation process 有权
标题翻译：双重杀菌过程
公开(公告)号：US06528402B2
公开(公告)日：2003-03-04
申请号：US09790513
申请日：2001-02-23
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/4933 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A dual salicidation process has the steps of: covering a sacrificial layer on the top of a polysilicon gate conductor; performing a thermal oxidization process to form a poly-oxide spacer on the sidewall of the polysilicon gate conductor; forming source/drain regions within the substrate at the outer lateral surfaces of the poly-oxide spacer;removing the sacrificial layer; performing a first salicidation process to convert the polysilicon gate conductor to a silicide gate conductor; performing a second salicidation process to form silicide structures upon the source/drain regions.
摘要翻译：双重酸化方法具有以下步骤：覆盖多晶硅栅极导体的顶部上的牺牲层; 进行热氧化处理以在所述多晶硅栅极导体的侧壁上形成多晶氧化物间隔物; 在所述多晶氧化物间隔物的外侧表面处在所述衬底内形成源/漏区;去除所述牺牲层; 执行第一次氧化处理以将多晶硅栅极导体转换成硅化物栅极导体; 进行第二次硫化处理以在源极/漏极区域上形成硅化物结构。

74. 发明授权

US06524939B2 Dual salicidation process 有权
公开(公告)号：US06524939B2
公开(公告)日：2003-02-25
申请号：US10051075
申请日：2002-01-22
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L213205
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/4933 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A dual salicidation process is used on a semiconductor substrate which has a gate dielectric, a polysilicon gate conductor patterned upon a predetermined area of the gate dielectric, a sacrificial layer patterned upon the polysilicon gate conductor, and LDD areas formed within the substrate at opposed sidewall of the polysilicon gate conductor. First, an insulator spacer on the sidewall of the polysilicon gate conductor and the sacrificial layer, and then the gate dielectric not covered by the insulator spacer is removed. Next, source/drain regions are formed within the substrate at the outer lateral surfaces of the insulator spacer. Thereafter, using salicidation process, silicide structures are formed upon the source/drain regions. After removing the sacrificial layer salicidation process is used again to convert the polysilicon gate conductor into a silicide gate conductor.

75. 发明授权

US06498064B2 Flash memory with conformal floating gate and the method of making the same 有权
标题翻译：具有保形浮栅的闪存及其制作方法
公开(公告)号：US06498064B2
公开(公告)日：2002-12-24
申请号：US09855941
申请日：2001-05-14
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A flash memory comprises a substrate having trenches formed therein. A tunneling oxide is formed on a surface of the substrate and adjacent to the trenches. A raised isolation fillers is formed in the trenches and protruding over an upper surface of the substrate, thereby forming a cavity between two adjacent raised isolation fillers. A floating gate is formed along a surface of the cavity to have a U-shaped structure in cross sectional view, wherein the high level of the U-shaped structure is the same with the one of the raised isolation fillers. An isolation structure is formed on the top of the raised isolation fillers and upper surface of the U-shaped structure. A dielectric layer is conformally formed on a surface of the floating gate and the isolation structure. A control gate is formed on the dielectric layer.
摘要翻译：闪存包括其中形成有沟槽的衬底。隧道氧化物形成在衬底的表面上并与沟槽相邻。在沟槽中形成凸起的隔离填料，并在衬底的上表面上突出，从而在两个相邻的凸起隔离填料之间形成空腔。沿着空腔的表面形成浮栅，以横截面图具有U形结构，其中高水平的U形结构与凸起隔离填料中的一个相同。在凸起的隔离填料的顶部和U形结构的上表面上形成隔离结构。电介质层共形地形成在浮动栅极和隔离结构的表面上。在电介质层上形成控制栅极。

76. 发明授权

US06399436B1 Method of making an electric conductive strip 有权
标题翻译：制造导电条的方法
公开(公告)号：US06399436B1
公开(公告)日：2002-06-04
申请号：US09664481
申请日：2000-09-18
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L21/76895 , H01L21/743 , H01L27/10885
摘要： A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface, and the barrier layer prevent the dopants from diffusing into the upper horizontal surface.
摘要翻译：一种用于制造导电条的方法包括沿屏障的表面，垂直表面和下水平表面形成掺杂介电层。然后，在掺杂电介质层上形成离子注入敏感性抗蚀剂。下一步是通过基本上垂直的注入将离子注入到离子注入敏感的抗蚀剂中，使得下部和上部水平表面上的离子注入的敏感性抗蚀剂是显影剂中的不溶部分，并且垂直表面可溶于显影剂。随后，通过使用显影剂除去垂直表面，然后除去附着在垂直表面上的掺杂介电层。接下来，使用热处理将掺杂介电层中的掺杂剂扩散到下水平表面中，并且阻挡层防止掺杂剂扩散到上水平表面。

77. 发明授权

US06383937B1 Method of fabricating a silicon island 有权
标题翻译：制造硅岛的方法
公开(公告)号：US06383937B1
公开(公告)日：2002-05-07
申请号：US09715475
申请日：2000-11-17
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/84
摘要： A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma. Since the etch-rate of the doped silicon is higher than the undoped silicon, the doped silicon is easily and rapidly etched first, as the undoped silicon portion is exposed, the etching rate is substantially decreased or stopped forming a thin foot underneath the silicon island.
摘要翻译：公开了一种用于制造半导体器件结构的方法，其包括在硅衬底上的器件下方的薄的脚电荷漏极。这些结构保留了SOI器件的高速运行。在各种实施方案中，本发明包括在半导体衬底上形成第一扩散阻挡层，将所述第一扩散阻挡层和所述硅衬底图案化到一定深度以形成沟槽，形成第二扩散阻挡层并使所述第二扩散阻挡层在沟槽的侧壁上形成第一间隔物。执行定向蚀刻以暴露沟槽侧壁的一部分。将掺杂剂引入所述暴露的侧壁中以在侧壁附近形成掺杂区域。使用卤素气体等离子体进行各向同性蚀刻。由于掺杂硅的蚀刻速率高于未掺杂的硅，所以首先容易且快速地蚀刻掺杂的硅，因为未掺杂的硅部分被暴露，蚀刻速率基本上减小或停止，在硅岛下方形成薄的底脚。

78. 发明授权

US06376885B1 Semiconductor structure with metal silicide and method for fabricated the structure 有权
标题翻译：具有金属硅化物的半导体结构及其制造方法
公开(公告)号：US06376885B1
公开(公告)日：2002-04-23
申请号：US09670210
申请日：2000-09-25
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2972
CPC分类号： H01L29/66515 , H01L21/28061 , H01L21/28123 , H01L29/41775 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method is directed to form a semiconductor device with silicide formed by a metal layer associated with a deposited silicon layer by providing a substrate. A field oxide layer is formed on a substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. A spacer is formed on a sidewall of the gate structure. The cap layer is removed to expose the gate layer, whereby a trench is formed. A silicon layer is deposited over the substrate. A refractory metal layer is deposited on the silicon layer. A silicide layer is formed by performing a thermal process to trigger a reaction between the silicon layer and the metal layer. The silicide layer is polished by CMP process using the field oxide layer as a polishing stop. As a result, the silicide fills the trench above the gate layer and the cavity between the spacer and the field oxide layer.
摘要翻译：一种方法是通过提供衬底形成具有由与沉积的硅层相关联的金属层形成的硅化物的半导体器件。在衬底上形成场氧化物层以限定有源区。栅极结构形成在有源区上，其中栅极结构在栅极层上具有栅极氧化物层，栅极层和覆盖层。场氧化物层的高度基本上等于盖层。在栅极结构的侧壁上形成间隔物。去除盖层以露出栅极层，从而形成沟槽。在衬底上沉积硅层。难熔金属层沉积在硅层上。通过进行热处理以触发硅层和金属层之间的反应来形成硅化物层。通过使用场氧化物层作为抛光停止的CMP工艺对硅化物层进行抛光。结果，硅化物填充了栅极层上方的沟槽和间隔物和场氧化物层之间的空腔。

79. 发明授权

US06309923B1 Method of forming the capacitor in DRAM 有权
标题翻译：在DRAM中形成电容器的方法
公开(公告)号：US06309923B1
公开(公告)日：2001-10-30
申请号：US09620068
申请日：2000-07-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3143 , H01L21/31604 , H01L27/10855 , H01L28/55 , H01L28/84
摘要： A method of forming a capacitor with a self-align structure on a substrate, the substrate including a word line and an active region, the method including the steps of forming a first dielectric layer on the active region and the word line with a planar top surface, creating a contact hole in the first dielectric layer with the self-align structure to expose portions of the active region and the word line, forming a conductive layer on the bottom of the contact hole, forming a polysilicon spacer on the sidewall of the contact hole, forming a dielectric spacer on the sidewall of the polysilicon spacer, filling the contact hole with a polysilicon bar, creating three sub-contact holes by etching back the polysilicon spacer and the polysilicon bar with part of the polysilicon spacer and the polysilicon bar remaining on the bottom, forming a hemispherical grain (HSG) layer on the surface of the sub-contact holes, depositing a second dielectric layer on the hemispherical grain, and forming a top electrode on the second dielectric layer.
摘要翻译：一种在衬底上形成具有自对准结构的电容器的方法，所述衬底包括字线和有源区，所述方法包括以下步骤：在所述有源区上形成第一电介质层，并在所述字线上形成平面顶部在第一电介质层中形成具有自对准结构的接触孔，以暴露有源区和字线的部分，在接触孔的底部形成导电层，在接触孔的侧壁上形成多晶硅间隔物接触孔，在多晶硅间隔物的侧壁上形成电介质间隔物，用多晶硅棒填充接触孔，通过用多晶硅间隔物和多晶硅棒的一部分蚀刻多晶硅间隔物和多晶硅棒来产生三个子接触孔残留在底部，在子接触孔的表面上形成半球状晶粒（HSG）层，在半球形晶粒上沉积第二介电层，并形成第二电介质层上的顶部电极。

80. 发明授权

US06297121B1 Fabrication method for capacitors in integrated circuits with a self-aligned contact structure 有权
标题翻译：具有自对准接触结构的集成电路中的电容器的制造方法
公开(公告)号：US06297121B1
公开(公告)日：2001-10-02
申请号：US09638299
申请日：2000-08-16
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L28/84
摘要： A method of forming a capacitor for use in high density DRAM circuits is described. A layer of silicon dioxide over an integrated circuit wafer having devices formed therein. A contact hole, which is larger at the top of the contact hole than at the bottom of the contact hole, is formed in the layer of silicon dioxide. A layer of polysilicon is then formed on the sidewalls and bottom of the contact hole. Silicon dioxide spacers are then formed on the polysilicon formed on the sidewalls of the contact hole so that a center cavity remains in the contact hole. The center cavity is then filled with polysilicon to form a center pillar which makes electrical contact with the polysilicon at the bottom of the contact hole. The silicon dioxide spacers are then etched away. A capacitor dielectric layer of silicon dioxide is then deposited on the substrate thereby covering the polysilicon pillar in the contact hole and the polysilicon on the sidewalls and bottom of the contact hole. A layer of polysilicon is then formed on the second layer of silicon dioxide to form the second capacitor plate. In one embodiment a layer of hemispherical grain, HSG, polysilicon is formed on the polysilicon forming the first capacitor plate to increase the capacitance.
摘要翻译：描述形成用于高密度DRAM电路的电容器的方法。在其上形成有器件的集成电路晶片上的二氧化硅层。在二氧化硅层中形成接触孔顶部比接触孔底部更大的接触孔。然后在接触孔的侧壁和底部上形成多晶硅层。然后在形成在接触孔的侧壁上的多晶硅上形成二氧化硅间隔物，使得中心腔保留在接触孔中。然后用多晶硅填充中心腔以形成与接触孔底部的多晶硅电接触的中心柱。然后将二氧化硅间隔物蚀刻掉。然后在衬底上沉积二氧化硅的电容器电介质层，从而覆盖接触孔中的多晶硅柱和接触孔的侧壁和底部上的多晶硅。然后在第二二氧化硅层上形成多晶硅层以形成第二电容器板。在一个实施例中，在形成第一电容器板的多晶硅上形成半球形晶粒HSG，多晶硅层以增加电容。

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