专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20080268165A1 Process for making a porous substrate of glass powder formed through flame spray pyrolysis 审中-公开
标题翻译：制造通过火焰喷雾热解形成的玻璃粉末的多孔基材的方法
公开(公告)号：US20080268165A1
公开(公告)日：2008-10-30
申请号：US11891519
申请日：2007-08-10
申请人： Curtis Robert Fekety , Yichun Connie Wang , Joseph Marc Whalen
发明人： Curtis Robert Fekety , Yichun Connie Wang , Joseph Marc Whalen
IPC分类号： C23C4/12
CPC分类号： C03C17/42 , B82Y5/00 , B82Y30/00 , C03C17/001 , C03C17/007 , C03C2217/425 , C03C2218/119 , C03C2218/15 , C03C2218/34 , C23C4/123
摘要： Inorganic porous substrates and methods of making inorganic porous substrates utilizing nanoparticles deposited onto a base substrate are described. The inorganic porous substrates are useful for biological applications, for example, biomolecule attachment such as DNA, RNA, protein and the like. The inorganic porous substrates are also useful for cell growth applications.
摘要翻译：描述了无机多孔基材和利用沉积在基底基材上的纳米颗粒制备无机多孔基材的方法。无机多孔基材可用于生物应用，例如生物分子附着如DNA，RNA，蛋白质等。无机多孔基材也可用于细胞生长应用。

72. 发明申请

US20050224979A1 CU INTERCONNECTS WITH COMPOSITE BARRIER LAYERS FOR WAFER-TO-WAFER UNIFORMITY 有权
标题翻译：具有复合阻挡层的CU互连用于波形到波长均匀性
公开(公告)号：US20050224979A1
公开(公告)日：2005-10-13
申请号：US10811860
申请日：2004-03-30
申请人： Amit Marathe , Connie Wang , Christy Woo
发明人： Amit Marathe , Connie Wang , Christy Woo
IPC分类号： H01L21/768 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846
摘要： A composite α-Ta/graded tantalum nitride/TaN barrier layer is formed in Cu interconnects with a structure designed for improved wafer-to-wafer uniformity, electromigration resistance and reliability, reduced contact resistance, and increased process margin. Embodiments include a dual damascene structure in a low-k interlayer dielectric comprising Cu and a composite barrier layer comprising an initial layer of TaN on the low-k material, a graded layer of tantalum nitride on the initial TaN layer and a continuous α-Ta layer on the graded tantalum nitride layer. Embodiments include forming the initial TaN layer at a thickness sufficient to ensure deposition of α-Ta, e.g., as at a thickness of bout 50 Å to about 100 Å. Embodiments include composite barrier layers having a thickness ratio of α-Ta and graded tantalum nitride: initial TaN of about 2.5:1 to about 3.5:1 for improved electromigration resistance and wafer-to-wafer uniformity.
摘要翻译：在Cu互连中形成复合α-Ta /分级氮化钽/ TaN阻挡层，其具有为提高晶片到晶片的均匀性，电迁移电阻和可靠性，降低的接触电阻和增加的工艺裕度而设计的结构。实施例包括在包含Cu的低k层间电介质中的双镶嵌结构和在低k材料上包含TaN的初始层的复合势垒层，初始TaN层上的氮化钽梯度层和连续的α-Ta 层叠在梯度氮化钽层上。实施方案包括以足以确保α-Ta沉积的厚度形成初始TaN层，例如在50至大约的厚度。实施例包括厚度比为α-Ta和梯度氮化钽的复合阻挡层：初始TaN为约2.5:1至约3.5:1，以提高电迁移阻力和晶片与晶片的均匀性。

73. 发明授权

US06861349B1 Method of forming an adhesion layer with an element reactive with a barrier layer 失效
标题翻译：用与阻挡层反应的元件形成粘合层的方法
公开(公告)号：US06861349B1
公开(公告)日：2005-03-01
申请号：US10145944
申请日：2002-05-15
申请人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Paul R. Besser , Matthew S. Buynoski , Pin-Chin Connie Wang
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76859 , H01L21/76873 , H01L21/76874
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元素进入阻挡材料层上的界面层，在界面层上沉积合金层。植入的第一合金元素与阻挡材料层反应，以增加对铜扩散的抗性。

74. 发明授权

US06703308B1 Method of inserting alloy elements to reduce copper diffusion and bulk diffusion 失效
标题翻译：插入合金元素以减少铜扩散和体扩散的方法
公开(公告)号：US06703308B1
公开(公告)日：2004-03-09
申请号：US09994400
申请日：2001-11-26
申请人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin , Alline F. Myers , Phin-Chin Connie Wang
发明人： Paul R. Besser , Matthew S. Buynoski , Sergey D. Lopatin , Alline F. Myers , Phin-Chin Connie Wang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76859 , H01L21/76867
摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.
摘要翻译：一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金元件进入阻挡材料层，以及在沉积通孔材料之后注入第二合金元件。植入的第一合金元素使得阻挡材料层更能抵抗铜扩散。植入的第二合金元件扩散到通孔材料的顶部界面并且减小从通孔材料的体积扩散。

75. 发明授权

US06657303B1 Integrated circuit with low solubility metal-conductor interconnect cap 有权
标题翻译：具有低溶解度金属导体互连帽的集成电路
公开(公告)号：US06657303B1
公开(公告)日：2003-12-02
申请号：US10016024
申请日：2001-12-12
申请人： Pin-Chin Connie Wang , Steven C. Avanzino
发明人： Pin-Chin Connie Wang , Steven C. Avanzino
IPC分类号： H01L3900
CPC分类号： H01L21/76849 , H01L21/76855 , H01L21/76858 , H01L21/76862 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。形成在半导体衬底上的器件电介质层。器件电介质层上的沟道介电层具有形成在其中的开口。屏障层对通道开口进行排列。导体芯填充阻挡层上的开口。铈导体互连帽设置在导电芯上方，在电介质层和铈导体互连帽上方具有覆盖层。

76. 发明授权

US06649034B1 Electro-chemical metal alloying for semiconductor manufacturing 有权
标题翻译：电化学金属合金化用于半导体制造
公开(公告)号：US06649034B1
公开(公告)日：2003-11-18
申请号：US09894191
申请日：2001-06-27
申请人： Minh Quoc Tran , Amit P. Marathe , Pin-Chin Connie Wang
发明人： Minh Quoc Tran , Amit P. Marathe , Pin-Chin Connie Wang
IPC分类号： C25B1500
CPC分类号： C25D21/14 , C25D3/58
摘要： The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A plurality of consumable remote secondary anodes at different voltages in the plating solution reservoir provides the metal ions for alloy plating.
摘要翻译：本发明提供了一种用于半导体晶片的合金电镀系统，其包括通过循环系统连接到电镀液储存器的电镀室。半导体晶片用作电镀室中具有惰性主阳极的阴极。在电镀溶液储存器中，多个在不同电压下的易消耗的远程次级阳极提供用于合金电镀的金属离子。

77. 发明授权

US06534865B1 Method of enhanced fill of vias and trenches 有权
标题翻译：增强通孔和沟槽填充的方法
公开(公告)号：US06534865B1
公开(公告)日：2003-03-18
申请号：US09880219
申请日：2001-06-12
申请人： Sergey D. Lopatin , Pin-Chin Connie Wang
发明人： Sergey D. Lopatin , Pin-Chin Connie Wang
IPC分类号： H01L21321
CPC分类号： H01L23/5226 , C23C18/1605 , C25D5/02 , H01L21/3212 , H01L21/76843 , H01L21/76847 , H01L21/76859 , H01L21/76873 , H01L21/76874 , H01L21/76877 , H01L21/76879 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method and apparatus for filling vias and trenches in integrated circuits is provided having a substrate with a device provided thereon. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening provided therein. A barrier layer lines the opening of the channel dielectric. A seed layer is deposited over the barrier layer. Portions of the seed layer are then doped with a material that inhibits the deposition of copper by electroplating or electroless deposition using ion implantation. A conductor core layer is deposited on the seed layer by electroplating or electroless deposition, filling the opening over the barrier layer. The inhibiting material on the doped seed layer creates a filling profile that allows for a more efficient, faster, void-free filling of the conductor core layer.
摘要翻译：提供一种用于在集成电路中填充过孔和沟槽的制造方法和装置，其具有设置在其上的装置的基板。在半导体衬底上形成器件电介质层。器件电介质层上的沟道电介质层具有设置在其中的开口。阻挡层对通道电介质的开口进行排列。种子层沉积在阻挡层上。然后通过使用离子注入的电镀或无电沉积来抑制铜的沉积的材料掺杂种子层的部分。通过电镀或无电沉积将导体芯层沉积在种子层上，填充阻挡层上的开口。掺杂种子层上的抑制材料产生填充轮廓，其允许导体芯层更有效，更快速，无空隙的填充。

78. 发明授权

US06462416B1 Gradated barrier layer in integrated circuit interconnects 有权
标题翻译：集成电路互连中的梯度势垒层
公开(公告)号：US06462416B1
公开(公告)日：2002-10-08
申请号：US09905469
申请日：2001-07-13
申请人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
发明人： Amit P. Marathe , Pin-Chin Connie Wang , Christy Mei-Chu Woo
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76873 , H01L23/53209 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer with an opening formed therein is formed on the semiconductor substrate. A barrier layer of barrier metal and barrier compound lines the opening, the barrier layer having a dielectric layer proximate and distal regions. The barrier layer has no barrier metal adjacent the dielectric layer proximate region and all barrier metal in the dielectric layer distal region, the barrier layer has all barrier compound adjacent the dielectric layer proximate region and no barrier compound before the dielectric layer distal region. A conductor core is over the barrier layer fills the opening and connects to the semiconductor device.
摘要翻译：提供了具有半导体器件的半导体衬底的集成电路及其制造方法。其中形成有开口的器件介电层形成在半导体衬底上。势垒金属和屏障化合物的阻挡层划分开口，阻挡层具有接近和远端区域的电介质层。阻挡层在电介质层邻近区域附近没有阻挡金属，并且介电层远侧区域中的所有势垒金属，阻挡层具有邻近电介质层邻近区域的所有阻挡化合物，并且在电介质层远端区域之前没有阻挡化合物。阻挡层之上的导体芯填充开口并连接到半导体器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式