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71. 发明授权

US08380898B2 Methods for main memory with non-volatile type memory modules 有权
标题翻译：具有非易失性存储器模块的主存储器的方法
公开(公告)号：US08380898B2
公开(公告)日：2013-02-19
申请号：US12832409
申请日：2010-07-08
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/12
CPC分类号： G06F13/4009 , G06F12/0638 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

72. 发明授权

US08375115B2 Methods, apparatus, and systems for integrated management, graphics and I/O control of server systems 有权
标题翻译：用于服务器系统的集成管理，图形和I / O控制的方法，设备和系统
公开(公告)号：US08375115B2
公开(公告)日：2013-02-12
申请号：US12030963
申请日：2008-02-14
申请人： Dwarka Partani , Sujith Arramreddy
发明人： Dwarka Partani , Sujith Arramreddy
IPC分类号： G06F15/173
CPC分类号： G06F3/023 , G09G5/006 , G09G2370/24 , H04L12/12 , Y02D50/40 , Y02D50/42
摘要： In one embodiment of the invention, a server system is disclosed for data processing having a printed circuit board with one or more processors to process data; a network interface controller coupled to the one or more processors; and a monolithic integrated circuit (IC) coupled to the one or more processors and the network interface controller. The network interface controller couples the server system to a network for remote client access to the server system. The monolithic integrated circuit couples a remote computer system to the server system via the network. The remote computer system includes a remote storage device, a remote display, a remote keyboard, and a remote mouse to allow remote control and management of the server system.
摘要翻译：在本发明的一个实施例中，公开了一种用于数据处理的服务器系统，其具有带有一个或多个处理器的印刷电路板来处理数据; 耦合到所述一个或多个处理器的网络接口控制器; 以及耦合到所述一个或多个处理器和所述网络接口控制器的单片集成电路（IC）。网络接口控制器将服务器系统耦合到网络，以便远程客户端访问服务器系统。单片集成电路通过网络将远程计算机系统耦合到服务器系统。远程计算机系统包括远程存储设备，远程显示器，远程键盘和远程鼠标，以允许服务器系统的远程控制和管理。

73. 发明授权

US08341572B1 Methods and apparatus for waveform based variational static timing analysis 有权
标题翻译：基于波形变分静态时序分析的方法和装置
公开(公告)号：US08341572B1
公开(公告)日：2012-12-25
申请号：US12331130
申请日：2008-12-09
申请人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
发明人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
摘要翻译：公开了一种基于波形变分静态时序分析的系统和方法。电路分为线性电路部分和非线性电路部分，并通过线性建模技术的组合建模在一起，形成可以由矩阵表示的线性方程组。矩阵形式的线性方程式可以由计算机容易地解决，使得可以将电路的输入引脚的输入波形顺序推送到电路的各种互连和逻辑网络到输出引脚。在波形推送的每个阶段获得输出电压波形，可用于执行静态时序分析。

74. 发明授权

US08341300B1 Systems for sustained read and write performance with non-volatile memory 有权
标题翻译：使用非易失性存储器持续读写性能的系统
公开(公告)号：US08341300B1
公开(公告)日：2012-12-25
申请号：US13162572
申请日：2011-06-16
申请人： Vijay Karamcheti , Shibabrata Mondal , Ajith Kumar
发明人： Vijay Karamcheti , Shibabrata Mondal , Ajith Kumar
IPC分类号： G06F3/00 , G06F13/12
CPC分类号： G06F13/1684 , G06F13/1642 , Y02D10/14
摘要： In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
摘要翻译：在本发明的一个实施例中，存储器系统包括耦合到存储器通道以共享总线的非易失性存储器件（NVMD）和耦合到多个NVMD之间的通信中的存储器通道的存储器控制器。每个NVMD一次独立地执行读，写或擦除操作。存储器控制器包括用于调度与存储器通道上的读取，写入和擦除操作相关联的控制和数据传输的信道调度器; 以及耦合到信道调度器的高优先级和低优先级队列。信道调度器优先处理在高优先级队列中等待低优先级队列中的操作的操作。信道调度器进一步优先考虑在高优先级队列或低优先级队列中等待在每个相应队列中等待的写入和擦除操作的读取操作。

75. 发明授权

US08326591B1 Synchronized envelope and transient simulation of circuits 有权
标题翻译：电路的同步包络和瞬态仿真
公开(公告)号：US08326591B1
公开(公告)日：2012-12-04
申请号：US11941904
申请日：2007-11-16
申请人： Qian Cai , Dan Feng , Bruce W. McGaughy , Jun Kong , Rendong Lin
发明人： Qian Cai , Dan Feng , Bruce W. McGaughy , Jun Kong , Rendong Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment of the invention, a method of simulating a circuit is disclosed including partitioning a circuit into a plurality of blocks, each of the plurality of blocks being radio-frequency blocks or non-radio frequency blocks; performing a first simulation of a first simulation type with the radio-frequency blocks to generate output waveforms of the radio-frequency blocks; performing a second simulation of a second simulation type with the non-radio-frequency blocks to generate output waveforms of the non-radio-frequency blocks where the second simulation type differs from the first simulation type; and synchronizing the first simulation and the second simulation together at one or more time steps to generate output waveforms for the circuit.
摘要翻译：在本发明的一个实施例中，公开了一种模拟电路的方法，包括将电路划分成多个块，所述多个块中的每一个是射频块或非射频块; 利用所述射频块执行第一仿真类型的第一仿真以产生所述射频块的输出波形; 对非射频块进行第二仿真类型的第二仿真，以产生第二仿真类型与第一仿真类型不同的非射频块的输出波形; 以及在一个或多个时间步骤一起同步所述第一仿真和所述第二仿真以产生所述电路的输出波形。

76. 发明授权

US08302046B1 Compact modeling of circuit stages for static timing analysis of integrated circuit designs 有权
标题翻译：用于集成电路设计的静态时序分析的电路级的紧凑建模
公开(公告)号：US08302046B1
公开(公告)日：2012-10-30
申请号：US12269037
申请日：2008-11-11
申请人： Igor Keller , King Ho Tam
发明人： Igor Keller , King Ho Tam
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Systems, apparatus, and methods of timing analysis with a multi-operating region gate model are disclosed, including modeling a logic gate with a constant direct current (DC) voltage source during a steady state region of operation; in response to a transition from the steady state region of operation, modeling the logic gate with a time-varying voltage dependent current source during a varying current region of operation; and, in response to a transition from the variable current region of operation, modeling the logic gate with a time-invariant voltage dependent current source during an asymptotic region of operation. Instantaneous output current provided by the time varying voltage dependent current source in the VCR region is responsive to time and the instantaneous output voltage of the logic gate. Instantaneous output current provided by the time-invariant voltage dependent current source in the AR region is responsive to the instantaneous output voltage of the logic gate.
摘要翻译：公开了具有多操作区域门模型的定时分析的系统，装置和方法，包括在稳定状态区域中用恒定直流（DC）电压源对逻辑门进行建模; 响应于从稳态操作区域的转变，在变化的当前操作区域期间用随时间变化的电压依赖电流源对逻辑门进行建模; 并且响应于来自可变电流操作区域的转变，在渐近的操作区域期间用不变的电压依赖电流源对逻辑门进行建模。由VCR区域中随时间变化的电压源提供的瞬时输出电流响应逻辑门的时间和瞬时输出电压。由AR区域中的不变电压依赖电流源提供的瞬时输出电流响应逻辑门的瞬时输出电压。

77. 发明授权

US07926011B1 System and method of generating hierarchical block-level timing constraints from chip-level timing constraints 有权
标题翻译：从芯片级定时约束产生分级块级时序约束的系统和方法
公开(公告)号：US07926011B1
公开(公告)日：2011-04-12
申请号：US11621915
申请日：2007-01-10
申请人： Oleg Levitsky , Chien-Chu Kuo , Dinesh Gupta
发明人： Oleg Levitsky , Chien-Chu Kuo , Dinesh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.
摘要翻译：一种设计集成电路的系统和方法，该集成电路能够导出从芯片级定时约束和分析导出的集成电路的各个块级电路的时序约束。块级定时约束是块级电路的输入和输出端口处的一个或多个逻辑时序约束点的形式。每个逻辑时序约束点指定用于通过端口对数据进行时钟源的时钟源，从输入端口向后指定数据传播延迟并从输出端口转发的延迟参数以及与数据路径相关联的任何定时异常。使用逻辑时序约束点，电路设计系统对每个块级电路进行独立的时序分析和优化。然后，系统将块级电路重新组装成可以实现时序闭合的修改的芯片级电路。

78. 发明授权

US07886238B1 Visual yield analysis of intergrated circuit layouts 有权
标题翻译：集成电路布局的视觉产量分析
公开(公告)号：US07886238B1
公开(公告)日：2011-02-08
申请号：US11564223
申请日：2006-11-28
申请人： Harsh Dev Sharma , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
发明人： Harsh Dev Sharma , Rajeev Srivastava , Srinivas R. Kommoori , Bharat Bhushan , Mithunjoy Parui , Albert Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.
摘要翻译：公开了基于产量分析优化布局的系统和方法。该方法包括生成具有两层或更多层导线互连的集成电路布局，以形成网段，并且具有一个或多个通孔接触层以将导线互连中的网段耦合在一起。该方法还包括对集成电路布局中的网段执行收益率分析，并使用多个不透明度级别对收益率分析的视觉描绘来显示净段以反映集成电路布局中的网段的收益率。

79. 发明授权

US07761836B1 Circuit autorouter with object oriented constraints 有权
标题翻译：具有面向对象约束的电路自动布线器
公开(公告)号：US07761836B1
公开(公告)日：2010-07-20
申请号：US11548288
申请日：2006-10-11
申请人： Ken Wadland , Sean Bergan , Charles W. Grant , Glendine Kingsbury , Randall Lawson , Jelena Radumilo-Franklin , Kota Sujan Reddy , Steve Russo , William Schilp , Davis Tsai , Keith Woodward , Richard Woodward , Jia Wu
发明人： Ken Wadland , Sean Bergan , Charles W. Grant , Glendine Kingsbury , Randall Lawson , Jelena Radumilo-Franklin , Kota Sujan Reddy , Steve Russo , William Schilp , Davis Tsai , Keith Woodward , Richard Woodward , Jia Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.
摘要翻译：在本发明的一个实施例中，公开了一种面向对象的自动布线器，用于在电路中布线网络。面向对象的自动布线器包括路由数据模型（RDM）; 至少一个路由引擎，例如单个连接路由器（SCR），地形（TOPO）转换引擎和细节几何（DETAIL）引擎，以及耦合在一起的命令和控制模块（CCM）。 RDM使用设计数据库读取和写入数据，以及读取一个或多个面向对象的设计约束。每个路由引擎具有至少一个动作来对设计数据库进行操作以提高电路对约束的依从性。 CCM控制电路中网络的总体路由过程，并且包括至少一个导向器来调用至少一个路由引擎以实现符合一个或多个约束。

80. 发明授权

US07761625B2 Methods for main memory with non-volatile type memory modules, and related technologies 有权
标题翻译：具有非易失性存储器模块的主存储器方法及相关技术
公开(公告)号：US07761625B2
公开(公告)日：2010-07-20
申请号：US11848040
申请日：2007-08-30
申请人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
发明人： Vijay Karamcheti , Kumar Ganapathy , Kenneth Alan Okin , Rajesh Parekh
IPC分类号： G06F13/12
CPC分类号： G06F13/4009 , G06F12/0638 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces.The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
摘要翻译：公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控制器。多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。存储器控制器控制对非易失性存储器模块的读取和写入访问。存储器插座通过印刷电路板迹线耦合到处理器插座。用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

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