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61. 发明授权

US4559460A Total security time-delay circuit 失效
标题翻译：总安全延时电路
公开(公告)号：US4559460A
公开(公告)日：1985-12-17
申请号：US479323
申请日：1983-03-28
申请人： Etienne Camus
发明人： Etienne Camus
IPC分类号： H03K17/28 , H03K17/60 , H03K19/007
CPC分类号： H03K17/28 , H03K17/601
摘要： A total security time-delay circuit useful in railway communications, for example, provides a series of output pulses after a specific minimum interval in response to a direct voltage applied to an input of the circuit, the minimum interval being maintained even in the event of circuit component malfunctions. A pulse generator connected to the circuit input provides a series of pulses to control a first contact breaker which switches the primary winding of a transformer to partially discharge a capacitor which is series-connected to the primary winding. The capacitor charges through a resistive network of a transformer secondary winding circuit which includes a second contact breaker having a control terminal connected to the transformer secondary winding and operable to provide output pulses when the capacitor discharge reaches a sufficient intensity. A grounded Zener diode connected to a junction of the resistive network and a switch terminal of the second contact breaker ensures that the time delay of the output pulses is not reduced below the minimum interval, even in the event of malfunctions in other circuit components.
摘要翻译：例如，在铁路通信中有用的总安全延时电路响应于施加到电路的输入的直流电压而在特定最小间隔之后提供一系列输出脉冲，即使在电路组件故障。连接到电路输入端的脉冲发生器提供一系列脉冲来控制第一接触断路器，该第一接触断路器切换变压器的初级绕组以部分地放电串联连接到初级绕组的电容器。电容器通过变压器次级绕组电路的电阻网络充电，该电路网络包括具有连接到变压器次级绕组的控制端子的第二接触断路器，并且可操作以在电容器放电达到足够的强度时提供输出脉冲。连接到电阻网络和第二接触断路器的开关端子的接地的齐纳二极管确保即使在其他电路部件发生故障的情况下，输出脉冲的时间延迟也不会降低到最小间隔以下。

62. 发明授权

US4554464A Propagation delay generator 失效
标题翻译：传播延迟发生器
公开(公告)号：US4554464A
公开(公告)日：1985-11-19
申请号：US413051
申请日：1982-08-30
申请人： Robert B. Davies , Ira Miller , Robert N. Dotson
发明人： Robert B. Davies , Ira Miller , Robert N. Dotson
IPC分类号： H03K5/13 , H03K17/28 , H03K3/017 , H03K5/04 , H03K17/56
CPC分类号： H03K17/28 , H03K5/13
摘要： A propagation delay generator is provided for controlling the duration of a bubble generate waveform of a bubble memory system. A first means is responsive to a digital input signal and provides an initializing signal to a current source. A capacitor is charged, responsive to an R-C time constant, by an increased voltage level prompted by the initializing signal. A second means is responsive to the charging signal in excess of that required to charge the capacitor. The second means thereby provides a digital output that is delayed from the digital input signal.
摘要翻译：提供传播延迟发生器用于控制气泡存储系统的气泡产生波形的持续时间。第一装置响应于数字输入信号并且向当前源提供初始化信号。响应于R-C时间常数，电容器被由初始化信号提示的增加的电压电平充电。第二装置响应于超过对电容器充电所需的充电信号。因此，第二装置提供从数字输入信号延迟的数字输出。

63. 发明授权

US4544257A Automatic exposure control for a camera shutter 失效
标题翻译：相机快门的自动曝光控制
公开(公告)号：US4544257A
公开(公告)日：1985-10-01
申请号：US597768
申请日：1984-04-06
申请人： Hideo Taka , Bernhard H. Andresen
发明人： Hideo Taka , Bernhard H. Andresen
IPC分类号： G03B7/083 , H03K17/28
CPC分类号： G03B7/083
摘要： The specification discloses an automatic shutter timing control for a camera. A voltage supply is applied to a capacitor (38). An electronic switch such as a PMOS gate (44) has conductive and non-conductive states and is connected across the capacitor (38). A pair of transistors (32) and (40) are interconnected in a current mirror configuration and are connected between the voltage supply and the capacitor (38) and are operable in conjunction with a charging resistor (30) such that the capacitor (38) may be charged to a predetermined voltage when the PMOS device (44) is in a non-conductive state. A transistor (54) is operable to receive an electrical control signal in order to sink current from the charging resistor (30) and to prevent current flow through the PMOS device (44). A comparator (42) is responsive to a predetermined voltage on the capacitor (38) to control the camera shutter.
摘要翻译：本说明书公开了一种用于相机的自动快门定时控制。电压供应给电容器（38）。诸如PMOS栅极（44）的电子开关具有导电和非导通状态并且跨过电容器38连接。一对晶体管（32）和（40）以电流镜配置互连，并连接在电压源和电容器（38）之间，并可与充电电阻（30）结合使用，使得电容器（38）当PMOS器件（44）处于非导通状态时，可以将其充电到预定电压。晶体管（54）可操作以接收电控制信号，以便从充电电阻（30）吸收电流并且防止电流流过PMOS器件（44）。比较器（42）响应电容器（38）上的预定电压来控制相机快门。

64. 发明授权

US4539712A Delay circuit 失效
标题翻译：延时电路
公开(公告)号：US4539712A
公开(公告)日：1985-09-03
申请号：US187842
申请日：1979-09-24
申请人： Tatsuo Ito
发明人： Tatsuo Ito
IPC分类号： H03J5/00 , H03J7/26 , H03J7/28 , H03K5/135 , H03K17/28 , H04B1/16 , H04B1/26
CPC分类号： H03J7/26 , H03K5/135
摘要： A delay circuit is disclosed having (32, 34), a flip-flop circuit (36), and circuits (30, 40) for maintaining reset states during the presence of a first signal (Xo, Yo) and a gate circuit (38) inputted with a second signal (Sd) and controlled to open and close by the output from the flip-flop circuit, and capable of obtaining a relatively long time of delay from the end of the first signal to the interruption of the output of the second signal, with ease in a digital manner even if produced as an integrated circuit. The delay circuit is suitable for use with the channel selection circuit in electronic tuning radio receivers.
摘要翻译： PCT No.PCT / JP79 / 00023 Sec。 371日期1979年9月24日 102（e）1979年9月24日PCT提交1979年1月30日PCT公布。公开号WO79 / 00564 公开了一种具有（32,34），触发器电路（36）和用于在存在第一信号（Xo，Yo）期间保持复位状态的电路（30,40）的延迟电路）和输入了第二信号（Sd）的门电路（38），并被触发器电路的输出控制为打开和关闭，并且能够从第一信号的结束获得相对长的延迟时间第二信号的输出的中断，即使作为集成电路生成，也以数字方式容易地进行。延迟电路适用于电子调谐无线电接收机中的信道选择电路。

65. 发明授权

US4538074A Power switch 失效
标题翻译：开关;电源开关
公开(公告)号：US4538074A
公开(公告)日：1985-08-27
申请号：US525864
申请日：1983-08-24
申请人： Jacob Fraden
发明人： Jacob Fraden
IPC分类号： H03K17/28 , H03K17/30 , H01H43/00
CPC分类号： H03K17/28 , H03K17/30 , Y10T307/832 , Y10T307/951 , Y10T307/957
摘要： An improved power switch circuit for turning on manually and for turning off either manually or automatically a battery operated electronic instrument. The circuit includes one manual momentary contact on/off switch, a bilateral switch or transmission gate, a microprocessor, and a capacitor that charges to a threshold level when the on/off switch is momentarily closed (on) and that discharges when either the on/off switch is momentarily closed again (off) or after a fixed amount of time has elapsed as determined by the microprocessor. The bilateral switch is switched on when the threshold potential is reached thereby preconditioning the on/off switch for turning the instrument off. The on/off switch can now be closed to discharge the capacitor or the microprocessor can discharge the capacitor thereby switching off the bilateral switch and preconditioning the on/off switch for again turning on the power to the electronic instrument.
摘要翻译：一种改进的电源开关电路，用于手动接通和手动或自动关闭电池供电的电子仪器。该电路包括一个手动瞬时触点开/关开关，双向开关或传输门，微处理器和电容器，当开/关开关瞬间关闭（on）时，充电至阈值电平，并且当on /关闭开关暂时关闭（关闭）或经过微处理器确定的固定时间量之后。当达到阈值电位时，双向开关接通，从而预先调节打开/关闭开关以关闭仪器。现在可以关闭开/关开关以放电电容器，或者微处理器可以放电电容器，从而关闭双向开关并预处理开/关开关，以再次打开电子仪器的电源。

66. 发明授权

US4412141A Three state loop keyer 失效
标题翻译：三态循环键控
公开(公告)号：US4412141A
公开(公告)日：1983-10-25
申请号：US217098
申请日：1980-12-16
申请人： Christian C. Jacobsen
发明人： Christian C. Jacobsen
IPC分类号： H03K17/66 , H03K17/04 , H03K17/28
CPC分类号： H03K17/667
摘要： A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor. When the AND gate is enabled and the output signal from the exclusive OR gate is the oscillator output signal, only one of these transistors is switched ON; and when the output of the oscillator gate is the inverted signal only the other transistor is switched ON. When the AND gate is disabled, neither transistor is switched on. For polar operation of this circuit, the opposite end of the transmission line is connected through a load resistor to voltage supply common. For neutral operation either the AND gate can be enabled and disabled or the load resistor can be connected to voltage supply positive or negative.
摘要翻译：描述了提供极性和中性接口的晶体管化键控电路。该电路包括振荡器，与门，异或门，变压器和两个类似的输出电路，每个都连接到变压器的次级。振荡器产生具有不对称占空比的高频二进制输出信号。振荡器的输出和低频数据信号被施加到与门。与门和另一个低频数据信号的输出被施加到异或门，该异或门的输出被放大并施加到变压器的初级。耦合到变压器的次级的每个输出电路包括用于将电源电压切换到传输线上的开关晶体管和用于控制开关晶体管的操作的峰值检测器。当与门使能并且异或门的输出信号是振荡器输出信号时，这些晶体管中只有一个接通; 当振荡器门的输出为反相信号时，只有另一个晶体管导通。当与门禁用时，晶体管都不会导通。对于该电路的极性运算，传输线的相对端通过负载电阻连接到电源电压。对于中性运行，与门可以使能和禁止，或负载电阻可以连接到电源正或负。

67. 发明授权

US4388538A Delay signal generating circuit 失效
标题翻译：延迟信号发生电路
公开(公告)号：US4388538A
公开(公告)日：1983-06-14
申请号：US191622
申请日：1980-09-29
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： H03K5/04 , H03K5/00 , H03K5/02 , H03K5/13 , H03K17/06 , H03K17/28 , H03K17/284 , H03K19/096 , H03K17/687 , H03K19/094
CPC分类号： H03K5/133 , H03K5/023 , H03K2005/00195
摘要： A digital circuit having a delay function which is operable with low power consumption and fabricated with a high-density integrated structure is disclosed. The circuit comprises a boot-strap circuit operable with a drain supply voltage and a source supply voltage, a first transistor of enhancement type having a drain connectable to the drain supply voltage and a source connected to an output node, a second transistor of depletion type having a drain connected to a boot node of the boot-strap circuit whose potential is operatively raised above the drain supply voltage and a source connected to the gate of the first transistor, and means for controlling the second transistor.
摘要翻译：公开了一种数字电路，其具有可以低功耗操作且具有高密度集成结构制造的延迟功能。该电路包括可与漏电源电压和源电源电压一起工作的引导电路，具有可连接到漏电源电压的漏极的增强型第一晶体管和连接到输出节点的源极，耗尽型第二晶体管具有连接到所述引导电路的引导节点的漏极，所述引导节点的电位在所述漏极电源电压之上操作地升高，以及连接到所述第一晶体管的栅极的源，以及用于控制所述第二晶体管的装置。

68. 发明授权

US4378503A Automotive backlight heater and timing control means 失效
标题翻译：汽车背光加热器和定时控制装置
公开(公告)号：US4378503A
公开(公告)日：1983-03-29
申请号：US367376
申请日：1982-04-12
申请人： Norman A. Rautiola
发明人： Norman A. Rautiola
IPC分类号： H01H43/00 , H03K17/28
CPC分类号： H01H43/00 , H03K17/28 , Y10T307/951
摘要： An electrical switching and timing assembly is shown having a manually actuatable switch selectively closable and openable, an associated electrical circuit has an input end and an output end, the input end is intended for connection to a source of electrical potential while the output end is intended for connection to an electrical load, the associated circuit has a timing circuit effective for opening the associated circuit within a preselected span of time after the associated circuit has been closed by the manually actuatable switch, the manually actuatable switch being effective for opening the associated circuit even before the expiration of the preselected span of time; the circuit means, manually actuatable switch means, the input and output ends and timing circuit are carried by unitized support structure.
摘要翻译：示出了电开关和定时组件，其具有可选择性地关闭和可打开的可手动致动的开关，相关联的电路具有输入端和输出端，输入端用于连接到电位源，而输出端旨在为了连接到电负载，相关联的电路具有定时电路，该定时电路在相关联的电路已经被可手动致动的开关闭合之后的预选的时间段内有效地打开相关联的电路，所述手动致动开关有效地打开相关联的电路即使在预选的时间段到期之前; 电路是手动启动开关装置，输入端和输出端和定时电路由单元化的支撑结构承载。

69. 发明授权

US4325101A Vital electronic time delay circuit 失效
标题翻译：重要的电子延时电路
公开(公告)号：US4325101A
公开(公告)日：1982-04-13
申请号：US106971
申请日：1979-12-26
申请人： Reed H. Grundy
发明人： Reed H. Grundy
IPC分类号： H01H47/00 , H03K17/28 , B61L21/06
CPC分类号： H01H47/002 , H03K17/28
摘要： A fail-safe electronic time delay circuit for providing a predetermined time delay period having an emitter-follower amplifier connectable to a source of recurrent signals, a voltage doubling rectifier for rectifying the amplified recurrent signals and for charging a capacitor which powers a tickler coil transistor oscillator, a pair of complementary switching transistors which are alternately rendered conductive by the a.c. oscillations of the transistor oscillator, a rectifier having a capacitor which is charged when one of the pair of complementary switching transistors is conductive and which is discharged through a vital relay when the other of the pair of complementary switching transistors is rendered conductive.
摘要翻译：一种用于提供具有可连接到反馈信号源的射极跟随放大器的预定时间延迟周期的故障安全电子时间延迟电路，用于整流放大的复现信号的电压倍增整流器，以及用于为tick线圈晶体管供电的电容器的充电振荡器，交替地交替地导通的一对互补开关晶体管所述晶体管振荡器的振荡，具有电容器的整流器，当所述一对互补开关晶体管中的一个导通时，所述电容器被充电，并且当所述一对互补开关晶体管中的另一个导通时通过重要继电器放电。

70. 发明授权

US4321687A Timing pulse generation 失效
标题翻译：定时脉冲发生
公开(公告)号：US4321687A
公开(公告)日：1982-03-23
申请号：US80873
申请日：1979-10-01
申请人： Raymond L. Parsons , Paul H. Paulsen
发明人： Raymond L. Parsons , Paul H. Paulsen
IPC分类号： H03K17/28 , G06F1/14 , H03K3/78 , H03K5/15 , G04F5/00 , G06F1/04
CPC分类号： H03K3/78 , H03K5/1502
摘要： Clock pulse plural cascade connected counters generate a plurality of patterns. Upon each clock pulse, the patterns in the plurality of counters are captured in a like plurality of registers. Each of the captured counts are then compared with one or more bit masks for determining identity. Detection of identity between any one of the plurality of masks with the selected ones of the registers results in the emission of a timing pulse. The initial counter states and the various mask values in the mask sets for the respective registers are program loaded. The apparatus can be computer monitored or can be programmed within a digital computer. Accordingly, the timing intervals are programmable by selecting diverse time-out lists.
摘要翻译：时钟脉冲多个级联连接的计数器产生多个模式。在每个时钟脉冲之后，多个计数器中的图案被捕获在相同的多个寄存器中。然后将每个捕获的计数与用于确定身份的一个或多个位掩码进行比较。通过使用所选择的一个寄存器来检测多个掩模中的任何一个的同一性，导致定时脉冲的发射。初始计数器状态和各个寄存器的掩码组中的各种掩码值被加载。该设备可以被计算机监视或者可以在数字计算机内编程。因此，通过选择不同的超时列表来编程定时间隔。

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