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61. 发明授权

US09430190B2 Fused multiply add pipeline 有权
标题翻译：熔融加倍管道
公开(公告)号：US09430190B2
公开(公告)日：2016-08-30
申请号：US14169864
申请日：2014-01-31
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Son Dao Trong , Michael Klein , Christophe Layer , Silvia M. Mueller
IPC分类号： G06F7/38 , G06F7/483 , G06F7/53 , G06F7/533 , G06F7/544
CPC分类号： G06F7/483 , G06F7/5312 , G06F7/5338 , G06F7/5443
摘要： A method for operating a fused-multiply-add pipeline in a floating-point unit of a processor is disclosed. A multiplication is initially performed between a first operand and a second operand in a multiplier block to obtain a set of partial product results. The partial product results are sent to a carry-save adder block. A partial product reduction is performed on the partial product results to generate a carry-save result having a sum term and a carry term. The carry-save result is then formatted to generate a carry-out bit. The carry-save result is added to a third operand to generate a final result.
摘要翻译：公开了一种用于在处理器的浮点单元中操作融合加法管线的方法。最初在乘法器块中的第一操作数和第二操作数之间执行乘法以获得一组部分乘积结果。部分乘积结果被发送到进位保存加法器块。对部分产品结果执行部分产品减少以产生具有和项和进位项的进位保存结果。然后格式化进位保存结果以生成进位位。进位保存结果被添加到第三个操作数以生成最终结果。

62. 发明授权

US09425798B2 Reconfigurable semiconductor device 有权
公开(公告)号：US09425798B2
公开(公告)日：2016-08-23
申请号：US14375344
申请日：2013-02-14
申请人： TAIYO YUDEN CO., LTD.
发明人： Masayuki Satou , Koshi Sato
IPC分类号： G01R31/02 , G01R31/26 , H03K19/177 , G11C29/00 , G06F7/38 , G11C11/34 , G11C8/10 , G11C7/00
CPC分类号： H03K19/177 , G01R31/2607 , G11C7/00 , G11C8/10 , G11C29/00 , H03K19/17728 , H03K19/1776
摘要： A semiconductor device capable of reconfiguration, including: a plurality of logic units which configure an array and are connected to each other, wherein each logic unit includes a pair of a first and a second memory cell units, each of the first and the second memory cell units operates as a logic element when truth value table data is written in, which is configured so that a logic calculation of an input value specified by a plurality of addresses is output to a data line, and/or operates as a connection element when truth value table data is written in, which is configured so that an input value specified by a certain address is output to a data line to be connected to an address of another memory cell unit, a latter stage of the first memory cell unit includes a sequential circuit which synchronizes with a clock, and the logic units include, for each pair of the first and the second memory cell units, a selection unit which selectively outputs an address to the first or the second memory cell unit in accordance with an operation switch signal.

63. 发明授权

US09411593B2 Processors, methods, systems, and instructions to consolidate unmasked elements of operation masks 有权
标题翻译：整合操作掩码的未屏蔽元素的处理器，方法，系统和指令
公开(公告)号：US09411593B2
公开(公告)日：2016-08-09
申请号：US13842730
申请日：2013-03-15
申请人： Intel Corporation
发明人： Ashish Jha
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30145 , G06F9/30018 , G06F9/30036
摘要： An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an operation mask consolidation instruction. The operation mask consolidation instruction is to indicate a source operation mask register, of the plurality of operation mask registers, and a destination storage location. The source operation mask register is to include a source operation mask that is to include a plurality of masked elements that are to be disposed within a plurality of unmasked elements. An execution unit is coupled with the decode unit. The execution unit, in response to the operation mask consolidation instruction, is to store a consolidated operation mask in the destination storage location. The consolidated operation mask is to include the unmasked elements from the source operation mask consolidated together. Other apparatus, methods, systems, and instructions are also disclosed.
摘要翻译：一方面的指令处理装置包括多个操作掩码寄存器。该装置还包括用于接收操作掩码合并指令的解码单元。操作掩码合并指令是指示多个操作掩码寄存器中的源操作掩码寄存器和目的地存储位置。源操作屏蔽寄存器包括源操作掩码，其包括要被布置在多个未屏蔽元件内的多个屏蔽元件。执行单元与解码单元耦合。执行单元响应于操作掩码合并指令，将合并的操作掩码存储在目的地存储位置中。合并操作掩码是将来自源操作掩码的未屏蔽元素合并在一起。还公开了其他装置，方法，系统和指令。

64. 发明授权

US09405683B2 Processor and memory control method for allocating instructions to a cache and a scratch pad memory 有权
标题翻译：用于将指令分配给高速缓存和临时存储器的处理器和存储器控制方法
公开(公告)号：US09405683B2
公开(公告)日：2016-08-02
申请号：US13045752
申请日：2011-03-11
申请人： Il Hyun Park , Soojung Ryu , Dong-Hoon Yoo , Dong Kwan Suh , Jeongwook Kim , Choon Ki Jang
发明人： Il Hyun Park , Soojung Ryu , Dong-Hoon Yoo , Dong Kwan Suh , Jeongwook Kim , Choon Ki Jang
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F12/08 , G06F9/50
CPC分类号： G06F12/08 , G06F9/5016 , G06F12/0871
摘要： A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
摘要翻译：提供了处理器和存储器管理方法。处理器包括处理器核心，经由单个端口向处理器核心传送数据的高速缓冲存储器，并存储由处理器核心访问的数据，以及将数据传送到处理器或从处理器收发的暂存器存储器（SPM）核心经由多个多端口中的至少一个。

65. 发明授权

US09396036B2 System and method for limiting the impact of stragglers in large-scale parallel data processing 有权
公开(公告)号：US09396036B2
公开(公告)日：2016-07-19
申请号：US14727753
申请日：2015-06-01
申请人： Google Inc.
发明人： Grzegorz Malewicz , Marian Dvorsky , Christopher B. Colohan , Derek P. Thomson , Joshua Louis Levenberg
IPC分类号： G06F9/30 , G06F15/00 , G06F9/50 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/54 , G06F17/30
CPC分类号： G06F9/5077 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/54 , G06F15/00 , G06F17/30584
摘要： A large-scale data processing system and method including a plurality of processes, wherein a master process assigns input data blocks to respective map processes and partitions of intermediate data are assigned to respective reduce processes. In each of the plurality of map processes an application-independent map program retrieves a sequence of input data blocks assigned thereto by the master process and applies an application-specific map function to each input data block in the sequence to produce the intermediate data and stores the intermediate data in high speed memory of the interconnected processors. Each of the plurality of reduce processes receives a respective partition of the intermediate data from the high speed memory of the interconnected processors while the map processes continue to process input data blocks an application-specific reduce function is applied to the respective partition of the intermediate data to produce output values.

66. 发明授权

US09383968B2 Math processing by detection of elementary valued operands 有权
标题翻译：通过检测基本值操作数进行数学处理
公开(公告)号：US09383968B2
公开(公告)日：2016-07-05
申请号：US14040370
申请日：2013-09-27
申请人： NVIDIA CORPORATION
发明人： Daniel Finchelstein , David Conrad Tannenbaum , Srinivasan (Vasu) Iyer
IPC分类号： G06F7/38 , G06F7/50 , G06F7/544
CPC分类号： G06F7/50 , G06F7/5443 , G06F2207/3884
摘要： One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing systems perform a great number of multiply-add operations. In a significant portion of these operations, the values of one or more of the operands are zero or 1.0. By detecting the occurrence of these elementary values, math operations can be greatly simplified, for example by eliminating multiply operations when one multiplicand is zero or 1.0 or eliminating add operations when one addend is zero. The simplified math operations resulting from detecting elementary valued operands provide significant savings in overhead power, dynamic processing power, and cycle time.
摘要翻译：本发明的一个实施例包括一种通过检测具有零或1.0等基本值的操作数简化算术运算的方法。计算机和图形处理系统执行大量的多重加法操作。在这些操作的重要部分中，一个或多个操作数的值为零或1.0。通过检测这些基本值的出现，可以大大简化数学运算，例如通过在一个被乘数为零或1.0时消除乘法运算，或者当一个加数为零时消除加法运算。检测基本值操作数导致的简化数学运算能够显着节省架空功耗，动态处理能力和循环时间。

67. 发明授权

US09354882B2 Methods and apparatus to manage partial-commit checkpoints with fixup support 有权
公开(公告)号：US09354882B2
公开(公告)日：2016-05-31
申请号：US14041170
申请日：2013-09-30
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.

68. 发明授权

US09348796B2 Arithmetic operation in a data processing system 有权
标题翻译：数据处理系统中的算术运算
公开(公告)号：US09348796B2
公开(公告)日：2016-05-24
申请号：US14031854
申请日：2013-09-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Klaus M. Kroener , Christophe J. Layer , Silvia M. Mueller , Kerstin Schelm
IPC分类号： G06F7/38 , G06F17/10 , G06F7/535 , G06F7/537
CPC分类号： G06F17/10 , G06F7/535 , G06F7/5375
摘要： An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.
摘要翻译：提出了数据处理单元中的优选地通过迭代数字积累的算术运算。迭代地计算算术运算的近似结果。同时计算算术运算的近似结果的至少两个补充值，并且根据最后一次迭代的结果从算术运算的近似结果和至少两个补充值中的一个值中选出最终结果步。

69. 发明授权

US09335996B2 Recycling error bits in floating point units 有权
标题翻译：浮点单位回收错误位
公开(公告)号：US09335996B2
公开(公告)日：2016-05-10
申请号：US13676796
申请日：2012-11-14
申请人： Intel Corporation
发明人： Helia Naeimi , Ralph Nathan , Daniel Sorin , Shih-Lien L. Lu
IPC分类号： G06F7/38 , G06F7/00 , G06F9/30
CPC分类号： G06F11/10 , G06F9/3001 , G06F9/30014 , G06F9/30101
摘要： A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.
摘要翻译：公开了一种用于回收浮点单元中的错误位的机构。本公开的系统包括可通信地耦合到存储器的存储器和处理装置。在一个实施例中，处理装置包括一个浮点单元（FPU），用于通过向FPU应用对浮点数输入的操作产生一个结果值，并使用该结果值产生一个误差值。 FPU还将结果值写入专用于从FPU的操作存储结果的处理装置的第一寄存器，并将该错误值写入专用于从FPU的操作存储错误的处理装置的第二寄存器。

70. 发明授权

US09323500B2 Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values 有权
公开(公告)号：US09323500B2
公开(公告)日：2016-04-26
申请号：US13785528
申请日：2013-03-05
申请人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
发明人： Brian Hickmann , Dennis Bradford , Thomas Fletcher
IPC分类号： G06F7/38 , G06F7/60 , G06F7/48 , G06F7/57 , G06F7/483 , G06F7/544 , G06F9/30 , G06F1/32
CPC分类号： G06F7/60 , G06F1/324 , G06F1/3243 , G06F7/48 , G06F7/483 , G06F7/5443 , G06F7/57 , G06F9/30 , G06F9/3001 , G06F2207/3884 , Y02D10/126 , Y02D10/152
摘要： In an embodiment, a fused multiply-add (FMA) circuit is configured to receive a plurality of input data values to perform an FMA instruction on the input data values. The circuit includes a multiplier unit and an adder unit coupled to an output of the multiplier unit, and a control logic to receive the input data values and to reduce switching activity and thus reduce power consumption of one or more components of the circuit based on a value of one or more of the input data values. Other embodiments are described and claimed.

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