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61. 发明申请

US20020167432A1 Programmable gain analog-to-digital converter 有权
标题翻译：可编程增益模数转换器
公开(公告)号：US20020167432A1
公开(公告)日：2002-11-14
申请号：US10142698
申请日：2002-05-08
发明人： Henry Tin-Hang Yung
IPC分类号： H03M001/18 , H03M001/14
CPC分类号： H03M1/18 , H03M1/0695 , H03M1/44 , H03M1/68 , H03M1/804
摘要： A multi-stage high-speed analog-to-digital converter with gain and offset adjustment. A programmable amplifier consisting of two capacitor arrays, and digitally controlled switching devices to manipulate an inputted analog signal. A four stage pipeline ADC provides an 8 bit digital output with redundancy and error correction.
摘要翻译：具有增益和偏移调整的多级高速模数转换器。由两个电容器阵列组成的可编程放大器和用于操纵输入的模拟信号的数字控制开关装置。四级流水线ADC提供8位数字输出，具有冗余和纠错功能。

62. 发明授权

US06404364B1 Multistage converter employing digital dither 有权
标题翻译：采用数字抖动的多级转换器
公开(公告)号：US06404364B1
公开(公告)日：2002-06-11
申请号：US09645003
申请日：2000-08-24
申请人： H. Scott Fetterman , David Arthur Rich
发明人： H. Scott Fetterman , David Arthur Rich
IPC分类号： H03M120
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/167 , H03M1/442
摘要： A multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A first stage receives the sampled analog signal as the analog input signal. Each stage provides a residue output, which is the analog input signal to a subsequent stage. The residue is the analog input signal to the stage, less the analog equivalent of the partial digital output from the stage, possibly with a gain change. A voltage range over which a sample of an analog signal can vary is defined by a lower limit and an upper limit. A lower comparator threshold is established within the voltage range. An upper comparator threshold is established within the voltage range, between the lower comparator threshold and the upper limit. The analog input to the stage is quantized based on the lower and upper comparator thresholds to generate a quantized sampled analog signal. When the quantizes sampled analog signal is between the lower and upper comparator thresholds, dither is added to the quantized sampled analog signal to produce the partial digital output. The partial digital outputs from each stage are provided to an error corrector circuit that removes redundancy and effects of the dither and generates the digital representation corresponding to the sampled analog input. The effect of dither is to improve the spurious free dynamic range (SFDR) of the digital representation of the analog input.
摘要翻译：一种用于将采样的模拟信号转换成相应的数字表示的多级转换器和方法。转换器的每个级接收模拟输入信号并产生部分数字输出。第一级接收采样的模拟信号作为模拟输入信号。每个阶段提供一个残留输出，这是后续阶段的模拟输入信号。剩余部分是到阶段的模拟输入信号，少于级的部分数字输出的模拟等效，可能增益变化。模拟信号的样本可以变化的电压范围由下限和上限定义。在电压范围内建立较低的比较器阈值。在较低的比较器阈值和上限之间的电压范围内建立较高的比较器阈值。基于较低和较高的比较器阈值对该级的模拟输入进行量化，以产生量化的采样模拟信号。当量化采样的模拟信号在下比较器阈值和上限比较器阈值之间时，抖动被加到量化的采样模拟信号上以产生部分数字输出。来自每个级的部分数字输出被提供给错误校正器电路，其消除抖动的冗余和影响，并产生对应于采样的模拟输入的数字表示。抖动的影响是改善模拟输入的数字表示的无杂散动态范围（SFDR）。

63. 发明授权

US06288663B1 Pipelined analog-to-digital converter with relaxed inter-stage amplifier requirements 有权
标题翻译：流水线模数转换器具有放松的阶段放大器要求
公开(公告)号：US06288663B1
公开(公告)日：2001-09-11
申请号：US09371416
申请日：1999-08-10
申请人： Richard Knight Hester , William Joseph Bright
发明人： Richard Knight Hester , William Joseph Bright
IPC分类号： H03M112
CPC分类号： H03M1/0695 , H03M1/442
摘要： This document describes a simple modification to the traditional pipelined analog-to-digital converter (ADC) architecture that reduces the signal swing of the inter-stage amplifier by a factor of two. This is a significant advantage when low power supply voltages limit the output range of operational amplifies. The modification requires no additional hardware and produces no additional power consumption.
摘要翻译：本文档描述了传统流水线模数转换器（ADC）架构的简单修改，可将两级放大器的信号摆幅降低一倍。当低电源电压限制运算放大器的输出范围时，这是一个显着的优势。该修改不需要额外的硬件，不产生额外的功耗。

64. 发明授权

US06172629B2 Multistage analog-to-digital converter employing dither 失效
标题翻译：采用抖动的多级模数转换器
公开(公告)号：US06172629B2
公开(公告)日：2001-01-09
申请号：US09025956
申请日：1998-02-19
申请人： H. Scott Fetterman
发明人： H. Scott Fetterman
IPC分类号： H03M120
CPC分类号： H03M1/0641 , H03M1/0695 , H03M1/167 , H03M1/442
摘要： There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.
摘要翻译：公开了一种用于将输入信号从一种形式转换成另一种形式的转换器。该转换器包括一个适于将信号切割成电平的分片电路。切片电路包括用于建立切片电平的至少一个阈值。抖动被用于在切片电路中改变至少一个切片电平。

65. 发明授权

US6166674A Analog to digital converter using several cascade-connected interpolation circuits 失效
标题翻译：模数转换器采用多个级联连接的内插电路
公开(公告)号：US6166674A
公开(公告)日：2000-12-26
申请号：US885959
申请日：1997-06-30
申请人： Marc Wingender , Stephane Le Tual
发明人： Marc Wingender , Stephane Le Tual
IPC分类号： H03M1/06 , H03M1/16 , H03M1/44 , H03M1/34 , H03M1/62
CPC分类号： H03M1/204 , H03M1/0682 , H03M1/0695 , H03M1/168
摘要： Disclosed is an analog to digital converter with several cascade-connected interpolation and selection circuits. The function of an interpolation circuit is to produce five pairs of output signals from three pairs of input signals and select three pairs from among the five pairs to apply them to the next stage. Each pair comprises two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of one pair being equal when the voltage Vin is equal to a reference voltage associated with this pair. There are five reference voltage associated with the five pairs. Among these five reference voltages, the three reference voltages (and therefore also the three corresponding pairs of signals) that most closely surround the input voltage Vin are selected. The reference voltages are increasingly closer together as the operation progresses in the succession of cascade-connected stages. The signals used to select the pairs of signals are used in a decoder that gives the bits of the analog-digital conversion.
摘要翻译：公开了具有几个级联连接的内插和选择电路的模数转换器。内插电路的功能是从三对输入信号产生五对输出信号，并从五对中选择三对，将其应用于下一级。每对包括两个插值信号，它们作为电压Vin的函数对称地和单调地变化，当电压Vin等于与该对相关联的参考电压时，一对信号相等。有五个参考电压与五对相关联。在这五个参考电压中，选择最接近于输入电压Vin的三个参考电压（因此也是三个对应的信号对）。随着连续级联连接阶段的操作进行，参考电压越来越近。用于选择信号对的信号用于给出模数转换位的解码器。

66. 发明授权

US5914682A Segmentwise operating digital-to-analog converter 失效
标题翻译：分段操作数模转换器
公开(公告)号：US5914682A
公开(公告)日：1999-06-22
申请号：US834804
申请日：1997-04-03
申请人： Yasunori Noguchi
发明人： Yasunori Noguchi
IPC分类号： H03M1/68 , H03L7/08 , H03M1/06 , H03M1/70 , H03M1/76
CPC分类号： H03M1/0695 , H03M1/682 , H03M1/765
摘要： A segmentwise-operating D/A converter has the first and second D/A conversion circuits. Input digital data containing a plurality of bits is divided into two segments. The digital data of one segment is processed by the first D/A conversion circuit to be converted into analog signal. The digital data of another segment is processed by the second D/A conversion circuit to be converted into analog signal. Outputs from the first and second D/A conversion circuits are added together. The full-scale value of the D/A conversion circuit of one segment is set to be more than the full-scale value of the D/A conversion circuit of an adjacent segment divided by the N-th power of two (N represents the number of bits contained in one segment).
摘要翻译：分段操作D / A转换器具有第一和第二D / A转换电路。输入包含多个位的数字数据被分成两段。一段数字数据由第一D / A转换电路处理，转换为模拟信号。另一段的数字数据由第二D / A转换电路处理，以转换为模拟信号。来自第一和第二D / A转换电路的输出被加在一起。一个段的D / A转换电路的满量程值被设置为大于相邻段的D / A转换电路的满量程除以2的N次方（N表示一个段中包含的位数）。

67. 发明授权

US4814767A Sub-ranging A/D converter with flash converter having balanced input 失效
标题翻译：具有平衡输入的带闪存转换器的子范围A / D转换器
公开(公告)号：US4814767A
公开(公告)日：1989-03-21
申请号：US106712
申请日：1987-10-08
申请人： John W. Fernandes , Gerald A. Miller , Andrew M. Mallinson
发明人： John W. Fernandes , Gerald A. Miller , Andrew M. Mallinson
IPC分类号： H03M1/14 , H03M1/00 , H03M1/34
CPC分类号： H03M1/0695 , H03M1/0682 , H03M1/162 , H03M1/363
摘要： A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possible a 14-bit output or an increased yield of 12-bit converters.

68. 发明授权

US4804960A Sub-ranging A/D converter with improved error correction 失效
标题翻译：子范围A / D转换器，具有改进的纠错
公开(公告)号：US4804960A
公开(公告)日：1989-02-14
申请号：US106714
申请日：1987-10-08
申请人： John W. Fernandes , Gerald A. Miller , Andrew M. Mallinson , Stephen R. Lewis
发明人： John W. Fernandes , Gerald A. Miller , Andrew M. Mallinson , Stephen R. Lewis
IPC分类号： H03M1/14 , H03M1/00 , H03M1/34
CPC分类号： H03M1/0695 , H03M1/0682 , H03M1/162 , H03M1/363
摘要： A 12-bit sub-ranging A/D converter which operates through four successive sub-ranging cycles with an 8:1 gain change between the cycles. The residue signal for each cycle is directed to a four-bit flash converter the output of which sets the latches for corresponding bit-current-sources of a DAC. The flash converter input circuit comprises identical residue and reference amplifiers driving symmetrical residue and reference networks for controlling the flash converter comparators. The DAC output for each cycle is compared with the analog input signal to produce a corresponding new residue signal. There are 15 bit-current-sources, three for the first cycle, and four for each of the last three cycles. The MSB of each group of four bit-current sources is an overlap bit having the same current weighting as the LSB of the preceding group. Setting of the overlap bit makes it possible to develop a correct output for the DAC for each of the 2nd through 4th cycles without altering bits already determined in previous cycles. The converter provides an optional 5th cycle making possible a 14-bit output or an increased yield of 12-bit converters.
摘要翻译：一个12位子范围A / D转换器，通过四个连续的子测距周期操作，周期之间的增益为8：1。每个周期的残留信号指向一个四位闪存转换器，其输出为DAC的相应位电流源设置锁存器。闪存转换器输入电路包括相同的残留和参考放大器，驱动对称的残留和参考网络，用于控制闪存转换器比较器。将每个周期的DAC输出与模拟输入信号进行比较，以产生相应的新的残留信号。有15个位电流源，第一个周期有三个，最后三个周期中有四个。每组4位电流源的MSB是具有与前一组的LSB相同的当前权重的重叠位。重叠位的设置使得可以在第2到第4个周期的每一个周期内为DAC开发正确的输出，而不改变在先前周期中已经确定的位。该转换器提供可选的第5个周期，使得14位输出或增加的12位转换器的产量成为可能。

69. 发明申请

US20190215003A1 PROGRAMMABLE TRIM FILTER FOR SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER COMPARATOR 审中-公开
公开(公告)号：US20190215003A1
公开(公告)日：2019-07-11
申请号：US16357753
申请日：2019-03-19
申请人： Avnera Corporation
发明人： Wai Lee , Garry N. Link
IPC分类号： H03M1/46 , H03M1/14 , H03M1/16 , H03M1/80 , H03M1/06 , H03M1/12
CPC分类号： H03M1/462 , H03M1/0626 , H03M1/0695 , H03M1/124 , H03M1/145 , H03M1/164 , H03M1/181 , H03M1/468 , H03M1/806
摘要： The disclosure includes a successive approximation register (SAR) analog to digital converter (ADC). The SAR ADC includes a sampling network to store a sample of an analog signal. The SAR ADC also includes a comparator to successively compare the sample to reference values to determine a digital value corresponding to the sample of the analog signal. The comparator employs a plurality of comparator preamplifiers. The comparator also includes a programmable trim filter. The programmable trim filter is selectively set to adjust a bandwidth of the comparator preamplifiers to a bandwidth value corresponding with a preamplifier settling time subceeding a preamplifier settling threshold.

70. 发明授权

US10075177B2 Semiconductor device 有权
公开(公告)号：US10075177B2
公开(公告)日：2018-09-11
申请号：US15797150
申请日：2017-10-30
申请人： Renesas Electronics Corporation
发明人： Yoshihiro Funato , Yasuo Morimoto
IPC分类号： H03M1/12 , H03M1/46 , H03M1/06
CPC分类号： H03M1/466 , H03M1/06 , H03M1/0695 , H03M1/468
摘要： A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator.The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

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