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61. 发明申请

US20160141416A1 SEMICONDUCTOR DEVICES AND FABRICATION METHODS 有权
标题翻译：半导体器件和制造方法
公开(公告)号：US20160141416A1
公开(公告)日：2016-05-19
申请号：US15003246
申请日：2016-01-21
申请人： Micron Technology, Inc.
发明人： Marcello Mariani , Carlo Pozzi
IPC分类号： H01L29/78 , H01L27/115 , H01L29/792 , H01L27/24 , H01L29/788 , H01L29/74 , H01L27/108
CPC分类号： H01L29/7827 , H01L21/2815 , H01L27/10805 , H01L27/11521 , H01L27/11568 , H01L27/2454 , H01L29/0649 , H01L29/0653 , H01L29/42376 , H01L29/495 , H01L29/4966 , H01L29/66363 , H01L29/66666 , H01L29/74 , H01L29/7889 , H01L29/7926
摘要： Methods of fabricating vertical devices are described, along with apparatuses and systems that include them. In one such method, a vertical device is formed at least partially in a void in a first dielectric material and a second dielectric material. Additional embodiments are also described.
摘要翻译：描述了制造垂直装置的方法以及包括它们的装置和系统。在一种这样的方法中，垂直装置至少部分地形成在第一介电材料和第二介电材料的空隙中。还描述了另外的实施例。

62. 发明授权

US09343507B2 Dual channel vertical field effect transistor including an embedded electrode 有权
标题翻译：双通道垂直场效应晶体管包括一个嵌入式电极
公开(公告)号：US09343507B2
公开(公告)日：2016-05-17
申请号：US14206196
申请日：2014-03-12
申请人： SanDisk 3D LLC
发明人： Seje Takaki
IPC分类号： H01L29/76 , H01L27/24 , H01L29/78 , H01L29/66 , H01L27/115 , H01L29/788 , H01L27/112 , H01L29/792 , H01L29/423 , H01L29/10 , H01L45/00 , H01L29/49
CPC分类号： H01L27/2481 , H01L27/11273 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/1033 , H01L29/42356 , H01L29/4925 , H01L29/4983 , H01L29/66666 , H01L29/7827 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A device is disclosed including one or more field effect transistors, each field effect transistor including: an elongated drain contact line including an electrically conductive material extending along a first horizontal direction; a drain including a first conductivity type semiconductor region overlaying the drain contact line; a source including a the first conductivity type semiconductor region located above the drain; and a gate extending vertically between the drain and the source. Each field effect transistor may include a first channel and a second channel, each including a second conductivity type
摘要翻译：公开了一种包括一个或多个场效应晶体管的器件，每个场效应晶体管包括：细长的漏极接触线，包括沿着第一水平方向延伸的导电材料; 漏极，包括覆盖所述漏极接触线的第一导电类型半导体区域; 源极，包括位于漏极上方的第一导电类型半导体区域; 以及在漏极和源极之间垂直延伸的栅极。每个场效应晶体管可以包括第一通道和第二通道，每个通道包括第二导电类型

63. 发明授权

US09343469B2 Three dimensional NAND flash with self-aligned select gate 有权
标题翻译：具有自对准选择门的三维NAND闪存
公开(公告)号：US09343469B2
公开(公告)日：2016-05-17
申请号：US13534295
申请日：2012-06-27
申请人： Jie Sun , Brian Cleereman , Minsoo Lee
发明人： Jie Sun , Brian Cleereman , Minsoo Lee
IPC分类号： H01L27/088 , H01L21/336 , H01L27/115 , G11C16/04 , H01L21/822 , H01L27/06 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/0483 , G11C2213/71 , H01L21/28282 , H01L21/8221 , H01L27/0688 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor material, and two or more memory cells, stacked vertically on top of the field effect transistor, and having channels that are formed in the pillar semiconductor of material.
摘要翻译：集成电路可以包括半导体材料的柱，具有形成在半导体材料的柱中的沟道的场效应晶体管，以及垂直于场效应晶体管的顶部堆叠的两个或更多个存储单元，并且具有形成在材料的柱状半导体中。

64. 发明授权

US09331090B2 Compact three dimensional vertical NAND and method of making thereof 有权
标题翻译：紧凑型三维垂直NAND及其制作方法
公开(公告)号：US09331090B2
公开(公告)日：2016-05-03
申请号：US14517122
申请日：2014-10-17
申请人： SANDISK TECHNOLOGIES INC.
发明人： Johann Alsmeier , Raghuveer S. Makala , Xiying Costa , Yanli Zhang
IPC分类号： H01L27/11 , H01L27/115 , H01L29/788 , H01L29/66 , G11C16/04 , H01L21/764 , H01L29/792
CPC分类号： H01L27/11551 , G11C16/04 , G11C16/0483 , H01L21/764 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7889 , H01L29/7926
摘要： A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.
摘要翻译： NAND器件具有至少3×3垂直NAND串的阵列，其中控制栅电极在阵列中是连续的，并且在阵列中不具有气隙或电介质填充沟槽。 NAND器件通过首先形成具有分离的下部选择栅极的下部选择栅极电平，然后形成包含多个NAND串部分的多个存储器件电平，然后在具有分离的上部选择的存储器件电平上形成上部选择栅极电平大门

65. 发明申请

US20160118397A1 NAND MEMORY STRINGS AND METHODS OF FABRICATION THEREOF 有权
标题翻译： NAND存储器及其制造方法
公开(公告)号：US20160118397A1
公开(公告)日：2016-04-28
申请号：US14523287
申请日：2014-10-24
申请人： SanDisk Technologies, Inc.
发明人： Sateesh KOKA , Raghuveer S. MAKALA , Yanli ZHANG , Senaka KANAKAMEDALA , Rahul SHARANGPANI , Yao-Sheng LEE , George MATAMIS
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
摘要翻译：制造单片三维存储器件的方法包括执行第一蚀刻以形成存储器开口和使用不同蚀刻工艺的第二蚀刻，以从存储器开口的底部去除半导体衬底的损坏部分。使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。另外的实施例包括提高存储器开口中的半导体沟道材料和底层半导体层之间的界面的质量，这可能被底部开口蚀刻损坏，包括通过从存储器的底表面的外延生长形成单晶半导体沟道材料暴露于底部开口蚀刻的开口和/或氧化表面，并在形成沟道材料之前去除氧化的表面。还公开了通过实施方式形成的单片三维存储器件。

66. 发明申请

US20160104721A1 VERTICAL TYPE MEMORY DEVICE 审中-公开
标题翻译：垂直型存储器件
公开(公告)号：US20160104721A1
公开(公告)日：2016-04-14
申请号：US14975703
申请日：2015-12-18
申请人： Kwang-Soo SEOL , Seong-Soon CHO
发明人： Kwang-Soo SEOL , Seong-Soon CHO
IPC分类号： H01L27/115 , H01L23/528 , H01L23/522
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L27/11565 , H01L27/1157 , H01L29/42332 , H01L29/66825 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
摘要翻译：一种半导体器件，包括：多个存储单元串; 有位以及将至少两个存储单元串耦合到位线的互连。存储单元串可以通过相应的互连耦合到相应的位线。替代的存储器单元串可以通过相应的不同互连耦合到不同的位线。

67. 发明授权

US09312396B2 Nonvolatile semiconductor memory transistor and method for manufacturing nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储晶体管及其制造方法
公开(公告)号：US09312396B2
公开(公告)日：2016-04-12
申请号：US14837615
申请日：2015-08-27
申请人： Unisantis Electronics Singapore Pte. Ltd.
发明人： Fujio Masuoka , Hiroki Nakamura
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L29/66
CPC分类号： H01L29/7889 , H01L21/28273 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line.
摘要翻译：非易失性半导体存储晶体管包括岛状半导体，其具有从硅衬底侧依次形成的源极区，沟道区和漏极区，浮置栅极，以围绕沟道区的外周的方式布置，插入在所述浮置栅极和所述沟道区域之间的隧道绝缘膜，控制栅极，其布置成围绕所述浮置栅极的外周，所述控制栅极具有介于所述控制栅极和所述浮置栅极之间的多晶硅间绝缘膜，以及控制栅极线路电连接到控制门并沿预定方向延伸。多晶硅间绝缘膜介于浮动栅极与控制栅极的下侧和内侧表面之间以及浮动栅极与控制栅极线的下表面之间。

68. 发明申请

US20160071878A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20160071878A1
公开(公告)日：2016-03-10
申请号：US14930504
申请日：2015-11-02
申请人： MICRON TECHNOLOGY, INC.
发明人： Neal L. Davis , David A. Kewley
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/792 , H01L29/7926
摘要： Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.
摘要翻译：一些实施例包括具有堆叠的半导体结构，所述堆叠包含交替的控制栅极材料和中间介电材料。通道材料面板沿着第一方向延伸穿过堆叠。所述面板将所述堆叠分成所述面板的第一侧上的第一部分和所述面板的第二侧上的第二部分。存储单元堆叠在通道材料面板和控制栅极材料之间。存储单元堆叠包括形状为具有指向通道材料面板的开口端的容器的单元电介质材料，并且在容器内包括电荷存储材料。一些实施例包括形成半导体结构的方法。

69. 发明授权

US09281318B2 Three dimensional memory structure 有权
公开(公告)号：US09281318B2
公开(公告)日：2016-03-08
申请号：US14813398
申请日：2015-07-30
申请人： Intel Corporation
发明人： Haitao Liu , Chandra V. Mouli , Krishna K. Parat , Jie Sun , Guangyu Huang
IPC分类号： H01L29/76 , H01L27/115 , H01L29/16 , H01L29/04 , G11C16/06
CPC分类号： H01L27/11582 , G11C16/06 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/04 , H01L29/16 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

70. 发明授权

US09269721B2 Memory device 有权
公开(公告)号：US09269721B2
公开(公告)日：2016-02-23
申请号：US14807879
申请日：2015-07-23
申请人： Kwang Soo Seol , JinTae Kang , Seong Soon Cho
发明人： Kwang Soo Seol , JinTae Kang , Seong Soon Cho
IPC分类号： G11C11/34 , G11C16/04 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11573 , H01L29/0676 , H01L29/413 , H01L29/42332 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

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