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1. 发明授权

US09460799B1 Recovery of partially programmed block in non-volatile memory 有权
标题翻译：在非易失性存储器中恢复部分编程的块
公开(公告)号：US09460799B1
公开(公告)日：2016-10-04
申请号：US14951347
申请日：2015-11-24
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Dana Lee , Zhenming Zhou
IPC分类号： G11C11/34 , G11C16/16 , G11C16/28
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/3418 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/76
摘要： Techniques for recovery of partially programmed blocks in non-volatile storage are disclosed. After programming memory cells in an open region of a partially programmed block, a fail bit count with respect to programming the memory cells is performed. If the fail bit count is above a threshold, then a recovery operation is performed of other memory cells in the partially programmed block. The recovery operation (such as erase) may remove charges that are trapped in the tunnel dielectric of memory cells in the open region of the partially programmed block. Note that this erase operation may be performed on memory cells in the open region that are already erased. The erase operation may remove trapped charges from the tunnel dielectric. In a sense, this “resets” the memory cells. Thus, the memory cells can now be programmed more effectively. Both programming and date retention may be improved.
摘要翻译：公开了用于恢复非易失性存储器中的部分编程块的技术。在将部分编程的块的开放区域中的存储器单元编程之后，执行关于编程存储器单元的故障位计数。如果故障比特数高于阈值，则对部分编程的块中的其他存储器单元进行恢复操作。恢复操作（例如擦除）可以去除被部分编程的块的开放区域中的存储器单元的隧道电介质中的电荷。注意，该擦除操作可以在已经被擦除的开放区域中的存储器单元上执行。擦除操作可以从隧道电介质中去除捕获的电荷。从某种意义上说，这个“复位”存储单元。因此，现在可以更有效地编程存储器单元。可以提高编程和日期保持。

2. 发明授权

US09099202B2 3D stacked non-volatile storage programming to conductive state 有权
标题翻译： 3D堆叠非易失性存储编程到导通状态
公开(公告)号：US09099202B2
公开(公告)日：2015-08-04
申请号：US13670233
申请日：2012-11-06
申请人： SanDisk Technologies Inc.
发明人： Andrei Mihnea , Xiying Costa , Yanli Zhang
IPC分类号： G11C11/56 , G11C16/10 , H01L27/11 , G11C16/04 , H01L27/115
CPC分类号： G11C11/5671 , G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582
摘要： Programming NAND strings in a 3D stacked storage device to a conductive state. Storage elements may be erased by raising their Vt and programmed by lowering their Vt. Programming may include applying a series of increasing voltages to selected bit lines until the selected memory cell is programmed. Unselected bit lines may be held at about ground, or close to ground. The selected word line may be grounded, or be held close to ground. Unselected word lines between the selected word line and the bit line may receive about the selected bit line voltage. Unselected word lines between the source line and the selected word line may receive about half the selected bit line voltage. Programming may be achieved without boosting channels of unselected NAND strings to inhibit them from programming. Therefore, program disturb associated with leakage of boosted channel potential may be avoided.
摘要翻译：将3D堆叠存储设备中的NAND串编程为导通状态。存储元件可以通过升高Vt并通过降低Vt进行编程而被擦除。编程可能包括对选定的位线施加一系列增加的电压，直到选定的存储单元被编程为止。未选择的位线可以保持在大约地面或靠近地面。所选择的字线可以接地，或者靠近地面。所选择的字线和位线之间的未被选择的字线可以接收所选位线电压。源极线和所选字线之间的未选字线可以接收大约一半的选定位线电压。可以在不增加未选择的NAND串的通道以阻止它们编程的情况下实现编程。因此，可以避免与提升的通道电位的泄漏相关的程序干扰。

3. 发明申请

US20150037950A1 COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF 有权
标题翻译：紧凑的三维垂直NAND及其制作方法
公开(公告)号：US20150037950A1
公开(公告)日：2015-02-05
申请号：US14517122
申请日：2014-10-17
申请人： Sandisk Technologies Inc.
发明人： Johann Alsmeier , Raghuveer S. Makala , Xiying Costa , Yanli Zhang
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L27/11551 , G11C16/04 , G11C16/0483 , H01L21/764 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7889 , H01L29/7926
摘要： A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.
摘要翻译： NAND器件具有至少3×3垂直NAND串的阵列，其中控制栅电极在阵列中是连续的，并且在阵列中不具有气隙或电介质填充沟槽。 NAND器件通过首先形成具有分离的下部选择栅极的下部选择栅极电平，然后形成包含多个NAND串部分的多个存储器件电平，然后在具有分离的上部选择的存储器件电平上形成上部选择栅极电平大门

4. 发明授权

US08885412B2 Erase operation with controlled select gate voltage for 3D non-volatile memory 有权
标题翻译：用三维非易失性存储器的受控选择栅极电压擦除操作
公开(公告)号：US08885412B2
公开(公告)日：2014-11-11
申请号：US14254586
申请日：2014-04-16
申请人： SanDisk Technologies Inc.
发明人： Haibo Li , Xiying Costa , Chenfeng Zhang
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
摘要翻译：用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极（SGD）和源极选择栅极（SGS）。在一种方法中，驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压，同时将擦除电压施加到位线或源极线。可以产生在选择栅极处更一致的栅极引起的漏极漏极（GIDL），以对NAND串的体进行充电。此外，可以用擦除电压来升高选择栅极电压，以避免导致退化的选择栅极之间的过多的漏极 - 栅极电压。选择栅极电压的升高可以从擦除操作的第一次擦除验证迭代开始，或者以预定或自适应确定的擦除验证迭代（例如基于编程擦除周期的数量）开始。

5. 发明授权

US09177673B2 Selection of data for redundancy calculation by likely error rate 有权
公开(公告)号：US09177673B2
公开(公告)日：2015-11-03
申请号：US14064887
申请日：2013-10-28
申请人： SanDisk Technologies Inc.
发明人： Deepak Raghu , Gautam A. Dusija , Chris Avila , Yingda Dong , Man Mui , Xiying Costa , Pao-Ling Koh
IPC分类号： G11C29/56 , G11C29/00 , G11C16/04 , G11C16/10 , G11C29/08 , G11C29/04
CPC分类号： G11C29/82 , G06F11/108 , G11C16/0483 , G11C16/10 , G11C29/08 , G11C29/822 , G11C29/838 , G11C2029/0411
摘要： Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.

6. 发明授权

US09047973B2 Group word line erase and erase-verify methods for 3D non-volatile memory 有权
标题翻译：用于3D非易失性存储器的组字线擦除和擦除验证方法
公开(公告)号：US09047973B2
公开(公告)日：2015-06-02
申请号：US14273900
申请日：2014-05-09
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Alex Mak , Johann Alsmeier , Man L Mui
IPC分类号： G11C11/34 , G11C16/34 , G11C16/14
CPC分类号： G11C16/3445 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/14 , G11C16/344 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution. In one approach, the control gate voltages are set differently for the different groups to slow down the storage elements which are expected to have a faster programming speed. An erase or inhibit status can be set for all groups together. In another approach, the control gate voltages are common for the different groups but an erase or inhibit status is set for each group separately.
摘要翻译：根据预期的擦除速度将存储元件分配给组的3D堆叠存储器件的擦除操作。然后根据它们的组擦除存储元件以提供更均匀的擦除深度和更严格的擦除分布。在一种方法中，对于不同的组，控制栅极电压的设置不同，以减慢期望具有更快编程速度的存储元件。可以将所有组一起设置为擦除或禁止状态。在另一种方法中，控制栅极电压对于不同的组是公共的，但是对于每个组分别设置擦除或禁止状态。

7. 发明申请

US20150121157A1 Selection of Data for Redundancy Calculation By Likely Error Rate 有权
标题翻译：冗余计算数据选择可能错误率
公开(公告)号：US20150121157A1
公开(公告)日：2015-04-30
申请号：US14064887
申请日：2013-10-28
申请人： SanDisk Technologies Inc.
发明人： Deepak Raghu , Gautam A. Dusija , Chris Avila , Yingda Dong , Man Mui , Xiying Costa , Pao-Ling Koh
IPC分类号： G11C29/08
CPC分类号： G11C29/82 , G06F11/108 , G11C16/0483 , G11C16/10 , G11C29/08 , G11C29/822 , G11C29/838 , G11C2029/0411
摘要： Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.
摘要翻译：多层存储器阵列中的层根据从其存储孔直径预测的可能的错误率进行分类。沿着高风险层中的字线存储的数据经受冗余操作（例如XOR），其中数据将沿着低风险层中的字线存储，使得两者的风险都较低。

8. 发明授权

US08908444B2 Erase for 3D non-volatile memory with sequential selection of word lines 有权
公开(公告)号：US08908444B2
公开(公告)日：2014-12-09
申请号：US13960360
申请日：2013-08-06
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Seung Yu , Roy E. Scheuerlein , Haibo Li , Man L. Mui
IPC分类号： G11C16/00 , G11C16/16 , G11C16/14 , G11C16/24 , G11C11/56 , G11C16/34 , H01L29/792 , H01L27/115
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/14 , G11C16/24 , G11C16/3445 , H01L27/11551 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.

9. 发明授权

US08879333B2 Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits 有权
公开(公告)号：US08879333B2
公开(公告)日：2014-11-04
申请号：US14290224
申请日：2014-05-29
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L Mui
IPC分类号： G11C11/34 , G11C16/34 , G11C16/14 , G11C16/16 , G11C11/56 , G11C16/04
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.

10. 发明申请

US20140269081A1 SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS 有权
标题翻译：具有选择性抑制通过位置的3D非易失性存储器的软擦除操作
公开(公告)号：US20140269081A1
公开(公告)日：2014-09-18
申请号：US14290224
申请日：2014-05-29
申请人： SanDisk Technologies Inc.
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/34 , G11C16/14
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障位。

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