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61. 发明申请

US20100295062A1 SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US20100295062A1
公开(公告)日：2010-11-25
申请号：US12676212
申请日：2009-07-03
申请人： Masao Uchida , Masashi Hayashi , Koichi Hashimoto
发明人： Masao Uchida , Masashi Hayashi , Koichi Hashimoto
IPC分类号： H01L29/78 , H01L29/24 , H01L21/04
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device includes: a semiconductor layer including silicon carbide, which has been formed on a substrate; a semiconductor region 15 of a first conductivity type defined on the surface of the semiconductor layer 10; a semiconductor region 14 of a second conductivity type, which is defined on the surface 10s of the semiconductor layer so as to surround the semiconductor region 15 of the first conductivity type; and a conductor 19 with a conductive surface 19s that contacts with the semiconductor regions 15 and 14 of the first and second conductivity types. On the surface 10s of the semiconductor layer, the semiconductor region 15 of the first conductivity type has at least one first strip portion 60 that runs along a first axis i. The width C1 of the semiconductor region 15 of the first conductivity type as measured along the first axis i is greater than the width A1 of the conductive surface 19s as measured along the first axis i. And the periphery of the conductive surface 19s crosses the at least one first strip portion 60, 61.
摘要翻译：半导体器件包括：已经形成在衬底上的包含碳化硅的半导体层; 限定在半导体层10的表面上的第一导电类型的半导体区域15; 限定在半导体层的表面10s上以包围第一导电类型的半导体区域15的第二导电类型的半导体区域14; 以及具有与第一和第二导电类型的半导体区域15和14接触的导电表面19s的导体19。在半导体层的表面10s上，第一导电类型的半导体区域15具有沿着第一轴线i延伸的至少一个第一条带部分60。沿着第一轴线i测量的第一导电类型的半导体区域15的宽度C1大于沿着第一轴线i测量的导电表面19s的宽度A1。并且导电表面19s的周边与至少一个第一条带部分60,61交叉。

62. 发明授权

US07829374B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07829374B2
公开(公告)日：2010-11-09
申请号：US12516858
申请日：2008-07-18
申请人： Masashi Hayashi , Kazuya Utsunomiya , Osamu Kusumoto
发明人： Masashi Hayashi , Kazuya Utsunomiya , Osamu Kusumoto
IPC分类号： H01L21/28 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7828 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7802 , Y10S438/931
摘要： A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.
摘要翻译：根据本发明的半导体器件包括具有碳化硅半导体层的碳化硅半导体衬底; 设置在碳化硅半导体层中并包含p型杂质的p型杂质区; 电连接到p型杂质区的p型欧姆电极; 设置在与所述p型杂质区相邻的所述碳化硅半导体层中的n型杂质区，并且包含n型杂质; 和与n型杂质区电连接的n型欧姆电极。 p型欧姆电极含有镍，铝，硅和碳的合金，n型欧姆电极含有钛，硅和碳的合金。

63. 发明授权

US07824995B2 SiC semiconductor device and method for manufacturing the same 有权
标题翻译： SiC半导体器件及其制造方法
公开(公告)号：US07824995B2
公开(公告)日：2010-11-02
申请号：US12071717
申请日：2008-02-26
申请人： Takeshi Endo , Tsuyoshi Yamamoto , Eiichi Okuno
发明人： Takeshi Endo , Tsuyoshi Yamamoto , Eiichi Okuno
IPC分类号： H01L29/72
CPC分类号： H01L29/7828 , H01L21/049 , H01L29/045 , H01L29/0847 , H01L29/1608 , H01L29/51 , H01L29/66068
摘要： A SiC semiconductor device includes: a SiC substrate having a main surface; a channel region on the substrate; first and second impurity regions on upstream and downstream sides of the channel region, respectively; a gate on the channel region through a gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 2.6×1020 cm−3. The interface provides a channel surface perpendicular to a (0001)-orientation plane.
摘要翻译： SiC半导体器件包括：具有主表面的SiC衬底; 衬底上的沟道区; 分别在通道区域的上游侧和下游侧的第一和第二杂质区域; 通过栅极绝缘膜在沟道区上形成栅极。用于在第一和第二杂质区域之间流动电流的沟道区域由施加到栅极的电压来控制。沟道区域和栅极绝缘膜之间的界面的氢浓度等于或大于2.6×1020cm-3。界面提供垂直于（0001）取向平面的通道表面。

64. 发明授权

US07808040B2 Semiconductor device and a method for manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07808040B2
公开(公告)日：2010-10-05
申请号：US11740727
申请日：2007-04-26
申请人： Christian Foerster
发明人： Christian Foerster
IPC分类号： H01L29/76
CPC分类号： H01L29/165 , H01L29/1054 , H01L29/161 , H01L29/42368 , H01L29/66431 , H01L29/66666 , H01L29/7782 , H01L29/7828
摘要： A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a channel formation region formed on a side wall and includes a mixture of a first semiconductor material, having a first lattice constant and a second semiconductor material with a second lattice constant differing from the first lattice constant, wherein a proportion of the second semiconductor material increases with increasing distance from the side wall.
摘要翻译：公开了一种半导体器件。在一个实施例中，半导体器件包括形成在侧壁上的沟道形成区域，并且包括具有第一晶格常数的第一半导体材料和具有不同于第一晶格常数的第二晶格常数的第二半导体材料的混合物，其中第二半导体材料的一部分随着与侧壁的距离的增加而增加。

65. 发明申请

US20100237457A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100237457A1
公开(公告)日：2010-09-23
申请号：US12724243
申请日：2010-03-15
申请人： Mitsuhiko KITAGAWA
发明人： Mitsuhiko KITAGAWA
IPC分类号： H01L29/08
CPC分类号： H01L27/088 , H01L29/0634 , H01L29/0856 , H01L29/0878 , H01L29/4236 , H01L29/7391 , H01L29/7394 , H01L29/7397 , H01L29/7813 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7831 , H01L29/7838
摘要： A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
摘要翻译：半导体器件包括：具有第一端部和第二端部的半导体层; 第一主电极，设置在第一端部上并与半导体层电连接; 第二主电极，设置在第二端部并与半导体层电连接; 第一栅电极，其经由第一栅极绝缘膜设置在由所述第一端部朝向所述第二端部形成的多个第一沟槽中; 以及第二栅电极，其经由第二栅极绝缘膜设置在由所述第二端部朝向所述第一端部形成的多个第二沟槽中。多个第一栅电极之间的间隔和多个第二栅电极之间的间隔为200nm以下。

66. 发明授权

US07776692B2 Semiconductor device having a vertical channel and method of manufacturing same 有权
标题翻译：具有垂直通道的半导体器件及其制造方法
公开(公告)号：US07776692B2
公开(公告)日：2010-08-17
申请号：US11702601
申请日：2007-02-06
申请人： Jae-man Yoon , Bong-soo Kim , Hyeoung-won Seo , Kang-yoon Lee
发明人： Jae-man Yoon , Bong-soo Kim , Hyeoung-won Seo , Kang-yoon Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/7828 , H01L27/10891 , H01L29/42356 , H01L29/66666
摘要： A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.
摘要翻译：提供一种半导体器件，其具有能够降低围绕有源柱的栅极与连接栅电极的字线之间的界面接触电阻的垂直沟道及其制造方法。半导体器件包括沿垂直于半导体衬底的表面的方向延伸的多个有源柱。字线结构形成在用于连接设置在同一列或列中的活动柱的外周上。顶部和底部源极/漏极区域相对于字线结构分别形成在有源支柱之上和之下。

67. 发明申请

US20100193800A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100193800A1
公开(公告)日：2010-08-05
申请号：US12665556
申请日：2009-05-11
申请人： Masao Uchida , Kazuya Utsunomiya , Koichi Hashimoto
发明人： Masao Uchida , Kazuya Utsunomiya , Koichi Hashimoto
IPC分类号： H01L29/24 , H01L23/52 , H01L29/772
CPC分类号： H01L29/812 , H01L23/544 , H01L29/045 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is fabricated on an off-cut semiconductor substrate 11. Each unit cell 10 thereof includes: a first semiconductor layer 12 on the surface of the substrate 11; a second semiconductor layer 16 stacked on the first semiconductor layer 12 to have an opening 16e that exposes first and second conductive regions 15 and 14 at least partially; a first conductor 19 located inside the opening 16e of the second semiconductor layer 16 and having a conductive surface 19s that contacts with the first and second conductive regions 15 and 14; and a second conductor 17 arranged on the second semiconductor layer 16 and having an opening 18e corresponding to the opening 16s of the second semiconductor layer 16. In a plane that is defined parallel to the surface of the substrate 11, the absolute value of a difference between the respective lengths of the second semiconductor layer 16 and the second conductor 18 as measured in the off-cut direction is greater than the absolute value of their difference as measured perpendicularly to the off-cut direction.
摘要翻译：半导体器件制造在截止半导体衬底11上。每个单电池10包括：在衬底11的表面上的第一半导体层12; 堆叠在第一半导体层12上以具有至少部分地暴露第一和第二导电区域15和14的开口16e的第二半导体层16; 第一导体19位于第二半导体层16的开口16e的内部，并且具有与第一和第二导电区域15和14接触的导电表面19s; 以及布置在第二半导体层16上并具有对应于第二半导体层16的开口16s的开口18e的第二导体17.在与衬底11的表面平行定义的平面中，差异的绝对值在沿切断方向测量的第二半导体层16和第二导体18的各自长度之间的距离大于垂直于偏离方向测量的它们的差的绝对值。

68. 发明申请

US20100181606A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20100181606A1
公开(公告)日：2010-07-22
申请号：US12665584
申请日：2008-06-17
申请人： Masaru Takaishi
发明人： Masaru Takaishi
IPC分类号： H01L27/10 , H01L29/78 , H01L27/088
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/66666 , H01L29/7803 , H01L29/7828 , H01L29/7831 , H01L29/7839
摘要： Provided is a semiconductor device having a high switching speed. A semiconductor device (20) is provided with an n-type epitaxial layer (2) having a plurality of trenches (3) arranged at prescribed intervals (b); an embedded electrode (5) formed on an inner surface of the trench (3) through a silicon oxide film (4) to embed each trench (3); and a metal layer (7), which is capacitively coupled with the embedded electrode (5) by being arranged above the embedded electrode (5) through a silicon oxide film (6). In the semiconductor device (20), a region between the adjacent trenches (3) operates as a channel (current path)(11). A current flowing in the channel (11) is interrupted by covering the region with a depletion layer formed at the periphery of the trenches (3), and the current is permitted to flow through the channel (11) by eliminating the depletion layer at the periphery of the trenches (3).
摘要翻译：提供了具有高开关速度的半导体器件。半导体器件（20）设置有具有以规定间隔（b）布置的多个沟槽（3）的n型外延层（2）。通过氧化硅膜（4）形成在所述沟槽（3）的内表面上以嵌入每个沟槽（3）的嵌入式电极（5）; 和通过氧化硅膜（6）布置在嵌入式电极（5）的上方，与嵌入式电极（5）电容耦合的金属层（7）。在半导体器件（20）中，相邻沟槽（3）之间的区域作为沟道（电流路径）（11）工作。在通道（11）中流动的电流通过用形成在沟槽（3）的周边的耗尽层覆盖该区域而被中断，并且通过消除沟道（11）中的耗尽层，允许电流流过沟道（11）沟槽（3）的周边。

69. 发明授权

US07745276B2 Method for manufacturing SiC semiconductor device 有权
标题翻译： SiC半导体器件的制造方法
公开(公告)号：US07745276B2
公开(公告)日：2010-06-29
申请号：US12068263
申请日：2008-02-05
申请人： Eiichi Okuno , Hiroki Nakamura , Naohiro Suzuki
发明人： Eiichi Okuno , Hiroki Nakamura , Naohiro Suzuki
IPC分类号： H01L21/8234
CPC分类号： H01L29/7828 , H01L29/045 , H01L29/0615 , H01L29/0619 , H01L29/0657 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7802 , H01L29/7811 , H01L29/7813
摘要： A method for manufacturing a SiC semiconductor device includes: preparing a SiC substrate having a (11-20)-orientation surface; forming a drift layer on the substrate; forming a base region in the drift layer; forming a first conductivity type region in the base region; forming a channel region on the base region to couple between the drift layer and the first conductivity type region; forming a gate insulating film on the channel region; forming a gate electrode on the gate insulating film; forming a first electrode to electrically connect to the first conductivity type region; and forming a second electrode on a backside of the substrate. The device controls current between the first and second electrodes by controlling the channel region. The forming the base region includes epitaxially forming a lower part of the base region on the drift layer.
摘要翻译：一种制造SiC半导体器件的方法包括：制备具有（11-20）取向表面的SiC衬底; 在衬底上形成漂移层; 在漂移层中形成基极区; 在所述基底区域中形成第一导电类型区域; 在所述基极区上形成沟道区，以在所述漂移层和所述第一导电类型区之间耦合; 在沟道区上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 形成电连接到所述第一导电类型区域的第一电极; 以及在所述衬底的背面上形成第二电极。该器件通过控制沟道区域来控制第一和第二电极之间的电流。形成基极区域包括外延地形成漂移层上的基极区域的下部。

70. 发明授权

US07723190B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07723190B2
公开(公告)日：2010-05-25
申请号：US11647691
申请日：2006-12-28
申请人： Gyu Gwang Sim , Jong Min Kim
发明人： Gyu Gwang Sim , Jong Min Kim
IPC分类号： H01L21/8234
CPC分类号： H01L29/66666 , H01L21/26586 , H01L29/0634 , H01L29/0653 , H01L29/42368 , H01L29/7828
摘要： Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.
摘要翻译：公开了一种具有提高集成度的垂直沟槽栅极结构的半导体器件及其制造方法。半导体器件包括在第一导电类型衬底上具有第二导电类型的外延层，该第一导电类型衬底具有有源区和隔离区，隔离区中的沟槽，在外延层中的第二导电类型的第一区，沟槽，沟槽中预定深度处的隔离层，沿着沟槽的上侧部分的栅极绝缘层，沟槽上部的栅极电极，有源区域中的主体区域，主体上的源极电极区域，位于栅电极的相对侧部的体区的上部的源极区域和位于衬底的背面的漏电极。

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