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1. 发明授权

US07829374B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07829374B2
公开(公告)日：2010-11-09
申请号：US12516858
申请日：2008-07-18
申请人： Masashi Hayashi , Kazuya Utsunomiya , Osamu Kusumoto
发明人： Masashi Hayashi , Kazuya Utsunomiya , Osamu Kusumoto
IPC分类号： H01L21/28 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7828 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7802 , Y10S438/931
摘要： A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.
摘要翻译：根据本发明的半导体器件包括具有碳化硅半导体层的碳化硅半导体衬底; 设置在碳化硅半导体层中并包含p型杂质的p型杂质区; 电连接到p型杂质区的p型欧姆电极; 设置在与所述p型杂质区相邻的所述碳化硅半导体层中的n型杂质区，并且包含n型杂质; 和与n型杂质区电连接的n型欧姆电极。 p型欧姆电极含有镍，铝，硅和碳的合金，n型欧姆电极含有钛，硅和碳的合金。

2. 发明申请

US20100055858A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20100055858A1
公开(公告)日：2010-03-04
申请号：US12516858
申请日：2008-07-18
申请人： Masashi Hayashi , Kazuya Utusnomiya , Osamu Kusumoto
发明人： Masashi Hayashi , Kazuya Utusnomiya , Osamu Kusumoto
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L21/0485 , H01L29/086 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7802 , Y10S438/931
摘要： A semiconductor device according to the present invention includes a silicon carbide semiconductor substrate having a silicon carbide semiconductor layer; a p-type impurity region provided in the silicon carbide semiconductor layer and including a p-type impurity; a p-type ohmic electrode electrically connected to the p-type impurity region; an n-type impurity region provided in the silicon carbide semiconductor layer adjacent to the p-type impurity region, and including an n-type impurity; and an n-type ohmic electrode electrically connected to the n-type impurity region. The p-type ohmic electrode contains an alloy of nickel, aluminum, silicon and carbon, and the n-type ohmic electrode contains an alloy of titanium, silicon and carbon.
摘要翻译：根据本发明的半导体器件包括具有碳化硅半导体层的碳化硅半导体衬底; 设置在碳化硅半导体层中并包含p型杂质的p型杂质区; 电连接到p型杂质区的p型欧姆电极; 设置在与所述p型杂质区相邻的所述碳化硅半导体层中的n型杂质区，并且包含n型杂质; 和与n型杂质区电连接的n型欧姆电极。 p型欧姆电极含有镍，铝，硅和碳的合金，n型欧姆电极含有钛，硅和碳的合金。

3. 发明授权

US08933463B2 Semiconductor element, semiconductor device, and power converter 有权
标题翻译：半导体元件，半导体器件和功率转换器
公开(公告)号：US08933463B2
公开(公告)日：2015-01-13
申请号：US13780876
申请日：2013-02-28
申请人： Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Koichi Hashimoto , Shun Kazama
发明人： Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Koichi Hashimoto , Shun Kazama
IPC分类号： H01L29/16 , H01L29/66 , H01L29/78 , H03K17/14 , H01L29/45
CPC分类号： H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7805 , H01L29/7827 , H01L29/7828 , H03K17/145
摘要： A semiconductor element including an MISFET exhibits diode characteristics in a reverse direction through an epitaxial channel layer. The semiconductor element includes: a silicon carbide semiconductor substrate of a first conductivity type, semiconductor layer of the first conductivity type, body region of a second conductivity type, source region of the first conductivity type, epitaxial channel layer in contact with the body region, source electrode, gate insulating film, gate electrode and drain electrode. If the voltage applied to the gate electrode is smaller than a threshold voltage, the semiconductor element functions as a diode wherein current flows from the source electrode to the drain electrode through the epitaxial channel layer. The absolute value of the turn-on voltage of this diode is smaller than the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.
摘要翻译：包括MISFET的半导体元件通过外延沟道层在相反方向上表现出二极管特性。半导体元件包括：第一导电类型的碳化硅半导体衬底，第一导电类型的半导体层，第二导电类型的主体区域，第一导电类型的源极区域，与身体区域接触的外延沟道层，源电极，栅极绝缘膜，栅电极和漏电极。如果施加到栅电极的电压小于阈值电压，则半导体元件用作二极管，其中电流从源电极通过外延沟道层流到漏电极。该二极管的导通电压的绝对值小于由体区和第一碳化硅半导体层形成的体二极管的导通电压。

4. 发明授权

US08283973B2 Semiconductor element, semiconductor device, and electric power converter 有权
标题翻译：半导体元件，半导体器件和电力转换器
公开(公告)号：US08283973B2
公开(公告)日：2012-10-09
申请号：US13389555
申请日：2010-08-09
申请人： Koichi Hashimoto , Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Shun Kazama
发明人： Koichi Hashimoto , Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Shun Kazama
IPC分类号： G05F3/02
CPC分类号： H01L29/7828 , H01L29/1608 , H01L29/66068 , H01L29/78 , H01L29/7838 , H02M7/5387 , Y02B70/1483
摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.
摘要翻译：包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的半导体层20，第一导电类型的体区30 第二导电类型，第一导电类型的源极和漏极区域40和75，与主体区域接触的外延沟道层50，源极和漏极电极45和70，栅极绝缘膜60和栅电极65.如果施加到MISFET的栅电极的电压小于阈值电压，半导体元件100用作二极管，其中电流通过外延沟道层50从源电极45流到漏极70。绝对值该二极管的导通电压小于由体区和第一硅碳化物形成的体二极管的导通电压的导通电压 e半导体层。

5. 发明申请

US20120057386A1 SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE, AND POWER CONVERTER 有权
标题翻译：半导体元件，半导体器件和电源转换器
公开(公告)号：US20120057386A1
公开(公告)日：2012-03-08
申请号：US13266271
申请日：2010-04-28
申请人： Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Koichi Hashimoto , Shun Kazama
发明人： Kazuhiro Adachi , Osamu Kusumoto , Masao Uchida , Koichi Hashimoto , Shun Kazama
IPC分类号： H02M7/537 , H01L29/24
CPC分类号： H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7805 , H01L29/7827 , H01L29/7828 , H03K17/145
摘要： A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a silicon carbide semiconductor substrate 10 of a first conductivity type, a semiconductor layer 20 of the first conductivity type, a body region 30 of a second conductivity type, a source region 40 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, a source electrode 45, a gate insulating film 60, a gate electrode 65 and a drain electrode 70. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.
摘要翻译：包括根据本发明的MISFET的半导体元件100的特征在于通过外延沟道层50在相反方向上具有二极管特性。半导体元件100包括第一导电类型的碳化硅半导体衬底10，半导体层20 第一导电类型的体区30，第一导电类型的源极区40，与体区接触的外延沟道层50，源电极45，栅极绝缘膜60，栅电极65和漏电极70.如果施加到MISFET的栅电极的电压小于阈值电压，则半导体元件100用作二极管，其中电流从源电极45流到漏电极70通过外延沟道层50.该二极管的导通电压的绝对值小于体二的导通电压的绝对值由所述体区和所述第一碳化硅半导体层形成。

6. 发明授权

US07846828B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07846828B2
公开(公告)日：2010-12-07
申请号：US12338395
申请日：2008-12-18
申请人： Osamu Kusumoto , Makoto Kitabatake , Masao Uchida , Kunimasa Takahashi , Kenya Yamashita , Masahiro Hagio , Kazuyuki Sawada
发明人： Osamu Kusumoto , Makoto Kitabatake , Masao Uchida , Kunimasa Takahashi , Kenya Yamashita , Masahiro Hagio , Kazuyuki Sawada
IPC分类号： H01L21/28 , H01L21/44
CPC分类号： H01L29/7828 , H01L21/046 , H01L21/0475 , H01L21/0485 , H01L21/30625 , H01L29/1029 , H01L29/105 , H01L29/1608 , H01L29/365 , H01L29/41766 , H01L29/66068 , H01L29/7838 , H01L29/812
摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.
摘要翻译：进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。因此，获得了退火几乎没有表面粗糙度的光滑表面。此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

7. 发明授权

US07462540B2 Silicon carbide semiconductor device and process for producing the same 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07462540B2
公开(公告)日：2008-12-09
申请号：US10553845
申请日：2005-01-28
申请人： Kunimasa Takahashi , Makoto Kitabatake , Kenya Yamashita , Masao Uchida , Osamu Kusumoto , Ryoko Miyanaga
发明人： Kunimasa Takahashi , Makoto Kitabatake , Kenya Yamashita , Masao Uchida , Osamu Kusumoto , Ryoko Miyanaga
IPC分类号： H01L21/00
CPC分类号： H01L21/046
摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).
摘要翻译：一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5）在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火碳层（5）。

8. 发明申请

US20060055027A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060055027A1
公开(公告)日：2006-03-16
申请号：US10536828
申请日：2004-09-06
申请人： Makoto Kitabatake , Osamu Kusumoto , Nasao Uchida , Kunimasa Takahashi , Kenya Yamashita
发明人： Makoto Kitabatake , Osamu Kusumoto , Nasao Uchida , Kunimasa Takahashi , Kenya Yamashita
IPC分类号： H01L23/34
CPC分类号： H01L23/3735 , H01L23/3672 , H01L23/4334 , H01L24/48 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2924/01004 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12032 , H01L2924/12036 , H01L2924/1301 , H01L2924/13055 , H01L2924/13062 , H01L2924/13063 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor apparatus includes a semiconductor chip 61 including a power semiconductor device using a wide band gap semiconductor, base materials 62 and 63, first and second intermediate members 65 and 68a, a heat conducting member 66, a radiation fin 67, and an encapsulating material 68 for encapsulating the semiconductor chip 61, the first and second intermediate member 65 and 68a and the heat conducting member 66. The tips of the base materials 62 and 63 work respectively as external connection terminals 62a and 63a. The second intermediate member 68a is made of a material with lower heat conductivity than the first intermediate member 65, and a contact area with the semiconductor chip 61 is larger in the second intermediate member 68a than in the first intermediate member.
摘要翻译：半导体装置包括半导体芯片61，其包括使用宽带隙半导体的功率半导体器件，基底材料62和63，第一和第二中间构件65和68a，导热构件66，辐射翅片67和封装用于封装半导体芯片61，第一和第二中间构件65和68a以及导热构件66的材料68。基材62和63的尖端分别作为外部连接端子62a和63a工作。第二中间构件68a由比第一中间构件65低导热性的材料制成，并且与第一中间构件相比，第二中间构件68a的与半导体芯片61的接触面积更大。

9. 发明授权

US06995396B2 Semiconductor substrate, semiconductor device and method for fabricating the same 有权
公开(公告)号：US06995396B2
公开(公告)日：2006-02-07
申请号：US10279119
申请日：2002-10-24
申请人： Kunimasa Takahashi , Masao Uchida , Makoto Kitabatake , Toshiya Yokogawa , Osamu Kusumoto , Kenya Yamashita , Ryoko Miyanaga
发明人： Kunimasa Takahashi , Masao Uchida , Makoto Kitabatake , Toshiya Yokogawa , Osamu Kusumoto , Kenya Yamashita , Ryoko Miyanaga
IPC分类号： H01L31/0312 , H01L29/80 , H01L31/112 , H01L29/76 , H01L27/095
CPC分类号： H01L29/365 , C30B25/02 , C30B29/36 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/02584 , H01L21/0262 , H01L21/02661 , H01L21/0445 , H01L29/0657 , H01L29/1608 , H01L29/66068
摘要： A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat δ-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

10. 发明授权

US06940127B2 Equipment for communication system and semiconductor integrated circuit device 有权
标题翻译：通信系统和半导体集成电路设备设备
公开(公告)号：US06940127B2
公开(公告)日：2005-09-06
申请号：US10631086
申请日：2003-07-31
申请人： Toshiya Yokogawa , Kunimasa Takahashi , Masao Uchida , Makoto Kitabatake , Osamu Kusumoto
发明人： Toshiya Yokogawa , Kunimasa Takahashi , Masao Uchida , Makoto Kitabatake , Osamu Kusumoto
IPC分类号： H01L21/82 , H01L27/06 , H01L29/10 , H01L29/15 , H01L29/24 , H01L29/36 , H01L29/772 , H01L29/812 , H01L29/872 , H03D7/12 , H03F3/60 , H01L29/76
CPC分类号： H03F3/601 , H01L21/8213 , H01L27/0605 , H01L29/105 , H01L29/157 , H01L29/1608 , H01L29/365 , H01L29/7725 , H01L29/812 , H01L29/872 , H03D7/125 , H03F2200/294
摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of δ-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of δ-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the δ-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.
摘要翻译：用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

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