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61. 发明申请

US20070034931A1 Systems and methods for memory structure comprising a PPROM and an embedded flash memory 有权
标题翻译：用于存储器结构的系统和方法，包括PPROM和嵌入式闪存
公开(公告)号：US20070034931A1
公开(公告)日：2007-02-15
申请号：US11203708
申请日：2005-08-15
申请人： Chao Wu
发明人： Chao Wu
IPC分类号： H01L29/76
CPC分类号： H01L27/112 , H01L21/8221 , H01L27/0688 , H01L27/11206 , H01L27/11286 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L27/11578
摘要： A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structure.
摘要翻译：结合嵌入式闪存和PPROM的内存结构。 PPROM可以用作存储器结构。闪存可用于例如空气替换单元或备用存储器或附加存储器单元。 PPROM单元堆叠在闪存单元的顶部，并且可以通过实现三维PPROM结构来增加PPROM密度。

62. 发明授权

US06891742B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06891742B2
公开(公告)日：2005-05-10
申请号：US10480247
申请日：2002-07-12
申请人： Yoh Takano , Shigeharu Matsushita
发明人： Yoh Takano , Shigeharu Matsushita
IPC分类号： G11C11/00 , H01L27/02 , H01L27/105 , H01L27/11 , H01L27/112 , H01L27/115 , H01L27/22 , H01L45/00 , G11C11/22
CPC分类号： H01L27/0207 , G11C11/005 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/1116 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11502 , H01L27/11509 , H01L27/228 , H01L27/24
摘要： A semiconductor memory device having a first memory including a bit line, a word line arranged to intersect with the bit line and a storage unit arranged between the bit line and the word line, and a second memory different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate in a stacked manner reducing the thickness in the height direction and attaining further miniaturization (thinning). Further, no wire having a large parasitic capacitance or solder is employed for connecting the first memory and the second memory, thereby enabling high-speed data transfer between the first memory and the second memory.
摘要翻译：一种具有第一存储器的半导体存储器件，包括位线，布置成与位线交叉的字线和布置在位线和字线之间的存储单元，以及与第一存储器不同类型的第二存储器。第一存储器和第二存储器以堆叠的方式形成在半导体衬底上，从而减小了高度方向的厚度并进一步小型化（变薄）。此外，没有使用具有大的寄生电容或焊料的电线来连接第一存储器和第二存储器，从而使得能够在第一存储器和第二存储器之间进行高速数据传送。

63. 发明授权

US10644021B2 Dense arrays and charge storage devices 有权
公开(公告)号：US10644021B2
公开(公告)日：2020-05-05
申请号：US15971293
申请日：2018-05-04
申请人： SANDISK TECHNOLOGIES LLC
发明人： Thomas H. Lee , Igor G. Kouznetsov
IPC分类号： H01L27/11582 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L27/115 , H01L27/11521 , H01L27/11556 , H01L27/11578 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/788 , H01L29/792 , H01L29/861 , G11C16/04 , H01L27/11551 , H01L27/11568 , H01L27/11558 , H01L27/11526 , H01L27/11573 , H01L29/16 , G11C16/10 , G11C16/14 , G11C16/26 , H01L29/06 , H01L29/51 , H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/532 , H01L27/11565 , H01L29/739 , H01L29/786 , H01L27/1158
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/115 , H01L27/11286 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/7881 , H01L29/7889 , H01L29/78642 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616 , G11C2211/5612 , H01L27/1158 , H01L27/12
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

64. 发明授权

US09922940B2 Semiconductor device including air gaps between interconnects and method of manufacturing the same 有权
公开(公告)号：US09922940B2
公开(公告)日：2018-03-20
申请号：US15242964
申请日：2016-08-22
申请人： TOSHIBA MEMORY CORPORATION
发明人： Takashi Watanabe , Takeshi Arakawa
IPC分类号： H01L23/00 , H01L27/112 , H01L23/528 , H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L23/562 , H01L21/76807 , H01L21/76819 , H01L21/7682 , H01L21/76843 , H01L21/76877 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L23/53295 , H01L27/11286 , H01L28/00
摘要： A semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, includes no portion provided between the interconnects, and is formed of a second insulating material different from the first insulating material.

65. 发明授权

US09793275B2 Multilayer circuit 有权
公开(公告)号：US09793275B2
公开(公告)日：2017-10-17
申请号：US13259177
申请日：2009-08-14
申请人： Dmitri Borisovich Strukov , Julien Borghetti
发明人： Dmitri Borisovich Strukov , Julien Borghetti
IPC分类号： H01L23/48 , H01L29/792 , H01L23/52 , H01L21/44 , H01L27/105 , H01L27/06 , H01L27/10 , H01L27/112 , H01L27/24
CPC分类号： H01L27/105 , H01L27/0688 , H01L27/101 , H01L27/112 , H01L27/11286 , H01L27/24
摘要： A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first overlying layer (215) formed on the base layer (205) and having a first routing section (210) and a second overlying layer (220) formed on the first overlying layer (215). The second overlying layer (220) has a second routing section (210) and is formed using the same set of masks. The first routing section (210) and the second routing section (210) form a unique electrical pathway (248) between a base via (247) and an element in an overlying layer. A method for forming a multilayer circuit is also provided.

66. 发明申请

US20170243835A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20170243835A1
公开(公告)日：2017-08-24
申请号：US15242964
申请日：2016-08-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Takashi WATANABE , Takeshi ARAKAWA
IPC分类号： H01L23/00 , H01L27/112 , H01L23/528 , H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L23/562 , H01L21/76807 , H01L21/76819 , H01L21/7682 , H01L21/76843 , H01L21/76877 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L23/53295 , H01L27/11286 , H01L28/00
摘要： In one embodiment, a semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, and is formed of a second insulating material different from the first insulating material.

67. 发明申请

US20160141295A1 ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMMING AND READING A MEMORY ARRAY COMPRISING THE SAME 有权
标题翻译：一次可编程存储器单元和编程和读取包含该存储单元的存储器阵列的方法
公开(公告)号：US20160141295A1
公开(公告)日：2016-05-19
申请号：US15005012
申请日：2016-01-25
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Wei-Zhe Wong , Hsin-Ming Chen
IPC分类号： H01L27/112 , G11C17/18 , G11C17/16
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.
摘要翻译：一次可编程（OTP）存储单元包括选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管。选择栅极晶体管具有第一栅极端子，第一漏极端子和第一源极端子。以下栅极晶体管具有耦合到第一漏极端子的第二栅极端子，第二漏极端子和第二源极端子。反熔丝变容二极管具有耦合到第二漏极端子的第三栅极端子，第三漏极端子和第三源极端子。选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管形成在衬底结构上。

68. 发明授权

US09147687B2 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09147687B2
公开(公告)日：2015-09-29
申请号：US14299495
申请日：2014-06-09
申请人： Cha-Won Koh , Hyun-Woo Kim , Jeon-Il Lee , Hyo-Sung Lee
发明人： Cha-Won Koh , Hyun-Woo Kim , Jeon-Il Lee , Hyo-Sung Lee
IPC分类号： H01L27/112 , H01L21/3065 , H01L21/283
CPC分类号： H01L27/11286 , G03F7/0002 , H01L21/283 , H01L21/3065 , H01L21/31144 , H01L21/32139 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582
摘要： Semiconductor devices and methods of fabricating the same are provided. The methods include preparing a template having a three dimensional (3D) stair type structure formed in intaglio, forming an imprint pattern having the stair type structure using the template, and simultaneously forming stair type patterns on a substrate using the imprint pattern.
摘要翻译：提供半导体器件及其制造方法。所述方法包括制备具有以凹版形成的三维（3D）楼梯型结构的模板，使用该模板形成具有楼梯型结构的压印图案，并且使用压印图案同时在基板上形成阶梯型图案。

69. 发明授权

US09136272B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09136272B2
公开(公告)日：2015-09-15
申请号：US14062497
申请日：2013-10-24
申请人： SK hynix Inc.
发明人： Sung Lae Oh
IPC分类号： H01L27/00 , H01L27/112 , H01L27/115 , G11C16/10
CPC分类号： H01L27/11286 , G11C16/10 , H01L27/11526 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor device may include a voltage supply unit suitable for supplying a voltage, a first conductive line coupled to the voltage supply unit, a second conductive line formed over the first conductive line, a voltage contact plug formed over the second conductive line, a voltage transmission line formed over the voltage contact plug, and a switching element suitable for switching the voltage transferred from the voltage transmission line.
摘要翻译：半导体器件可以包括适于提供电压的电压供应单元，耦合到电压供应单元的第一导线，形成在第一导线上的第二导线，形成在第二导线上的电压接触插塞，传输线形成在电压接触插头上，以及开关元件，适于切换从电压传输线传输的电压。

70. 发明申请

US20150243366A1 ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMING AND READING A MEMORY ARRAY COMPRISING THE SAME 有权
标题翻译：一个可编程存储器单元和用于编程和读取包含该存储器单元的存储器阵列的方法
公开(公告)号：US20150243366A1
公开(公告)日：2015-08-27
申请号：US14697652
申请日：2015-04-28
申请人： eMemory Technology Inc.
发明人： Meng-Yi Wu , Chih-Hao Huang , Hsin-Ming Chen
IPC分类号： G11C17/16 , H01L27/112 , H01L29/78 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , H01L23/5252 , H01L27/101 , H01L27/11206 , H01L27/11286 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal.
摘要翻译：本发明提供一种包括选择栅极晶体管，随后的栅极晶体管和反熔丝变容二极管的一次性可编程（OTP）存储单元。选择栅极晶体管具有分别耦合到第一漏极端子和第一源极端子的第一栅极端子，第一漏极端子，第一源极端子和两个第一源极/漏极扩展区域。以下栅极晶体管具有分别耦合到第二漏极端子和第二源极端子的两个第二源极/漏极延伸区域的第二栅极端子，第二漏极端子，耦合到第一漏极端子的第二源极端子。反熔丝变容二极管具有第三栅极端子，第三漏极端子，耦合到第二漏极端子的第三源极端子和与第三漏极端子和第三源极端子耦合的第三源极/漏极扩展区域，用于短路第三漏极端子和第三源终端。

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