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61. 发明授权

US07317244B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07317244B2
公开(公告)日：2008-01-08
申请号：US10341463
申请日：2003-01-14
申请人： Yasufumi Uchida , Yoshimi Egawa
发明人： Yasufumi Uchida , Yoshimi Egawa
IPC分类号： H01L23/02
CPC分类号： H01L24/48 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/49 , H01L24/73 , H01L24/85 , H01L25/0657 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05124 , H01L2224/05155 , H01L2224/05552 , H01L2224/05553 , H01L2224/05554 , H01L2224/05644 , H01L2224/05655 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4845 , H01L2224/48465 , H01L2224/48471 , H01L2224/48472 , H01L2224/48644 , H01L2224/48655 , H01L2224/4911 , H01L2224/49171 , H01L2224/49429 , H01L2224/49433 , H01L2224/73265 , H01L2224/78301 , H01L2224/85205 , H01L2224/8592 , H01L2224/85951 , H01L2225/06506 , H01L2225/0651 , H01L2225/06568 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/0103 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/15311 , H01L2924/181 , H01L2924/20648 , H01L2924/20649 , H01L2224/78 , H01L2924/00 , H01L2924/00011 , H01L2924/00012 , H01L2924/20755 , H01L2924/20756 , H01L2924/2075 , H01L2924/20754
摘要： In a semiconductor device having a semiconductor chip mounted on a printed circuit board, the semiconductor chip has a plurality of electrodes and the printed circuit board has a plurality of conductive patterns. Metallic plated layers are formed on the electrodes of the semiconductor chip. The metallic plated layers on the electrodes of the semiconductor chip are electrically connected with the conductive patterns of the printed circuit board by metallic wires.
摘要翻译：在具有安装在印刷电路板上的半导体芯片的半导体器件中，半导体芯片具有多个电极，印刷电路板具有多个导电图案。金属镀层形成在半导体芯片的电极上。半导体芯片的电极上的金属镀层通过金属线与印刷电路板的导电图案电连接。

62. 发明授权

US07298040B2 Wire bonding method and apparatus for integrated circuit 有权
标题翻译：集成电路的接线方法和装置
公开(公告)号：US07298040B2
公开(公告)日：2007-11-20
申请号：US11177700
申请日：2005-07-08
申请人： William P. Cornelius
发明人： William P. Cornelius
IPC分类号： H01L23/498
CPC分类号： H01L24/48 , H01L23/49816 , H01L23/50 , H01L23/645 , H01L24/06 , H01L24/45 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05624 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/48233 , H01L2224/48472 , H01L2224/48624 , H01L2224/49052 , H01L2224/49174 , H01L2224/49175 , H01L2224/49431 , H01L2224/49433 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/10253 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H05K1/0231 , H05K1/112 , H05K2201/10545 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal-paths. Other methods and apparatuses are also described.
摘要翻译：引线接合方法和装置在本文中描述。在本发明的一个方面，示例性装置包括设置在IC器件的表面上的多个导电触头，多个导电触点设置在至少两行中，多个第一返回路径通过一些所述多个导电触点，通过所述多个导电触点中的一些形成的多个信号路径，并且其中所述多个第一返回路径中的至少一个被放置在所述多个信号路径的每个预定数量之间。还描述了其它方法和装置。

63. 发明申请

US20070103003A1 Circuit apparatus and fabrication method for circuit apparatus 失效
标题翻译：电路装置的电路装置及其制造方法
公开(公告)号：US20070103003A1
公开(公告)日：2007-05-10
申请号：US11591994
申请日：2006-11-01
申请人： Takeshi Onodera
发明人： Takeshi Onodera
IPC分类号： H02J1/10 , H02J3/38
CPC分类号： G06F1/26 , H01L2224/05554 , H01L2224/49175 , H01L2224/49433 , Y10T29/49124 , Y10T307/305 , Y10T307/391 , Y10T307/615
摘要： Disclosed herein is a circuit apparatus including: plural modules having functions which can be substituted for each other; a function allocation section configured to set a one-on-one corresponding relationship between a plurality of predetermined functions and the plural modules in response to a control signal inputted thereto and allocate the functions coordinated in accordance with the one-on-one relationship individually to the modules; and first power inputting sections configured to input power supplies to be supplied to the modules. The apparatus further includes: second power inputting sections configured to input power supplies each corresponding to at least one of the functions; and a connection section configured to connect at least some of the first power inputting sections and the second power inputting sections so that each of the power supplies inputted by the second power inputting sections is supplied to that one of the modules to which a function corresponding to the power supply is allocated.
摘要翻译：本发明公开了一种电路装置，包括：多个模块，具有能够彼此替代的功能; 功能分配单元，被配置为响应于输入的控制信号，在多个预定功能与多个模块之间设置一对一的对应关系，并将根据一对一关系协调的功能分别分配到模块; 以及第一电力输入部，被配置为输入要供给到所述模块的电源。该装置还包括：第二电力输入部分，被配置为输入各自对应于至少一个功能的电源; 以及连接部，其被配置为连接所述第一电力输入部和所述第二电力输入部中的至少一部分，使得由所述第二电力输入部输入的每个电力供应到所述模块中的与分配电源。

64. 发明申请

US20070045872A1 Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts 有权
标题翻译：具有用于连接到插入器基板的中间触点的微电子器件以及包含具有中间触点的微电子器件的相关方法
公开(公告)号：US20070045872A1
公开(公告)日：2007-03-01
申请号：US11217629
申请日：2005-08-31
申请人： Setho Fee
发明人： Setho Fee
IPC分类号： H01L23/52
CPC分类号： H01L24/06 , H01L21/563 , H01L23/3114 , H01L23/4951 , H01L23/49816 , H01L24/03 , H01L24/48 , H01L24/49 , H01L2224/0401 , H01L2224/05554 , H01L2224/48091 , H01L2224/4824 , H01L2224/49433 , H01L2224/73203 , H01L2224/81801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.
摘要翻译：具有中间触点的微电子器件以及包含具有中间触点的微电子器件的相关方法在本文中公开。根据本发明的一个实施例构造的封装的微电子器件包括附接到互连衬底的微电子管芯。微电子管芯包括电耦合到多个端子的集成电路。每个端子通过单独的引线接合电耦合到管芯上相应的第一接触。管芯上的每个第一触点通过诸如焊球的导电耦合器电耦合到互连衬底上的对应的第二触点。

65. 发明申请

US20070034993A1 Semiconductor assembly and packaging for high current and low inductance 有权
标题翻译：半导体组装和封装大电流和低电感
公开(公告)号：US20070034993A1
公开(公告)日：2007-02-15
申请号：US11204645
申请日：2005-08-15
申请人： Bernhard Lange
发明人： Bernhard Lange
IPC分类号： H01L23/495
CPC分类号： H01L23/49541 , H01L23/49548 , H01L23/645 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L2223/6611 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/2919 , H01L2224/32245 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/48644 , H01L2224/49111 , H01L2224/49113 , H01L2224/49171 , H01L2224/49431 , H01L2224/49433 , H01L2224/73265 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/0665 , H01L2924/07025 , H01L2924/2065 , H01L2224/78 , H01L2924/00 , H01L2924/00012
摘要： A device comprising a semiconductor chip (110) having a side edge (111) and a plurality of metal bond pads (120, 121) near the edge; the pads are aligned to form rows (130, 131) parallel to the edge. The device further includes a leadframe (100) having leads (140 . . . ) oriented with one end (140a . . . ) towards the chip edge and spaced from it by a gap (150); the chip is attached to the leadframe. Ends of selected leads are connected by a metal cross bar (160) parallel to the chip edge. Substantially parallel bond wires (170) are crossing the gap to connect each chip pad either to the crossbar or to a non-selected lead end. In a preferred lead arrangement, the selected leads alternate with non-selected leads.
摘要翻译：一种装置，包括具有侧边缘（111）和靠近边缘的多个金属接合焊盘（120,121）的半导体芯片（110）衬垫对齐以形成平行于边缘的行（130,131）。所述装置还包括引线框架（100），所述引线框架（100）具有朝向所述芯片边缘并且由间隙（150）与所述引线框架（100）间隔开的引线（140 ...）。芯片连接到引线框。所选导线的端部通过平行于芯片边缘的金属横杆（160）连接。基本上平行的接合线（170）正在穿过间隙，以将每个芯片焊盘连接到横杆或未选择的引线端。在优选的引线装置中，所选择的引线与未选择的引线交替。

66. 发明授权

US07165316B2 Methods for manufacturing resistors using a sacrificial layer 有权
标题翻译：使用牺牲层制造电阻器的方法
公开(公告)号：US07165316B2
公开(公告)日：2007-01-23
申请号：US10827860
申请日：2004-04-20
申请人： Joseph Fjelstad
发明人： Joseph Fjelstad
IPC分类号： H01C17/06
CPC分类号： H01L21/568 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L23/3107 , H01L23/3121 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L24/85 , H01L24/97 , H01L25/18 , H01L2221/68377 , H01L2224/05554 , H01L2224/05599 , H01L2224/32245 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4847 , H01L2224/48472 , H01L2224/48475 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85001 , H01L2224/85051 , H01L2224/85444 , H01L2224/92 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/181 , H01L2924/18165 , H01L2924/19043 , H01L2924/19107 , H01L2924/3011 , H01L2224/85 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： An electrical resistor is made by providing a sacrificial layer and conductive pads disposed on a first surface of the sacrificial layer. An electrically resistive material is deposited over the pads and on the first surface of the sacrificial layer to form at least one unit including the resistive material and the pads. At least part of the sacrificial layer is then removed so as to expose one or more of the pads.
摘要翻译：通过提供牺牲层和设置在牺牲层的第一表面上的导电焊盘来制造电阻器。电阻材料沉积在焊盘之上和牺牲层的第一表面上以形成包括电阻材料和焊盘的至少一个单元。然后去除牺牲层的至少一部分，以暴露一个或多个焊盘。

67. 发明授权

US07148567B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07148567B2
公开(公告)日：2006-12-12
申请号：US11078585
申请日：2005-03-14
申请人： Yasuo Moriguchi , Shintaro Mori , Fumihiko Terayama , Hirokazu Komoriya
发明人： Yasuo Moriguchi , Shintaro Mori , Fumihiko Terayama , Hirokazu Komoriya
IPC分类号： H01L23/34 , H01L23/52 , H01L25/16
CPC分类号： H01L24/06 , H01L23/49575 , H01L23/50 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48253 , H01L2224/49113 , H01L2224/49175 , H01L2224/49433 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01037 , H01L2924/01068 , H01L2924/01074 , H01L2924/01088 , H01L2924/10161 , H01L2924/10162 , H01L2924/14 , H01L2924/15173 , H01L2924/19043 , H01L2924/19107 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a–40e, 41a–41e and 42a–42d), a plurality of LEADs (50a–50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a–60e and 61a–61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a–40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a–50d).
摘要翻译：半导体集成电路器件具有分别设置有多个PAD（40a〜40e，41a〜41e，42a〜42d）的两个半导体集成电路芯片（20,30），多个LEAD（50a -50d）设置在半导体集成电路芯片的阵列周围，以及多个接合线（60a-60e和61a-61d）。多个接合线被连接成不跨越一个半导体集成电路芯片（30），并且允许另一半导体集成电路芯片（20）的PAD（40a〜40e）与LEAD（50a- 50 d）。

68. 发明申请

US20060244150A1 Memory Packages Having Stair Step Interconnection Layers 有权
公开(公告)号：US20060244150A1
公开(公告)日：2006-11-02
申请号：US11381357
申请日：2006-05-02
申请人： Joseph Fjelstad
发明人： Joseph Fjelstad
IPC分类号： H01L23/48
CPC分类号： G11C5/04 , B82Y10/00 , G01R31/2822 , G11C5/063 , H01L23/13 , H01L23/3114 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/4985 , H01L23/5389 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6627 , H01L2223/6633 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/49433 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/1903 , H01L2924/19039 , H01L2924/3011 , H01L2924/3025 , H01P3/08 , H01P5/028 , H05K1/024 , H05K1/0243 , H05K2201/0191 , H05K2201/09154 , H05K2201/09727 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.

69. 发明授权

US07120069B2 Electronic circuit package 失效
标题翻译：电子电路封装
公开(公告)号：US07120069B2
公开(公告)日：2006-10-10
申请号：US10786008
申请日：2004-02-26
申请人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
发明人： Nobuyasu Kanekawa , Hirokazu Ihara , Masatsugu Akiyama , Kiyoshi Kawabata , Hisayoshi Yamanaka , Tetsuya Okishima
IPC分类号： G11C11/00
CPC分类号： H01L24/49 , G11C5/04 , G11C5/06 , H01L23/50 , H01L23/538 , H01L23/5386 , H01L24/48 , H01L25/0652 , H01L25/18 , H01L2224/48091 , H01L2224/48227 , H01L2224/49433 , H01L2224/73265 , H01L2924/00014 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/01055 , H01L2924/01074 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/15183 , H01L2924/15787 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.
摘要翻译：一种电子设备，其包括布线基板和布线基板上形成的多个半导体裸芯片。半导体裸芯片包括用于处理数据的处理器和具有用于检测处理器的故障的检查功能的电路。

70. 发明申请

US20060186528A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060186528A1
公开(公告)日：2006-08-24
申请号：US10516417
申请日：2003-05-16
申请人： Toshio Sasaki , Fujio Ito , Hiromichi Suzuki
发明人： Toshio Sasaki , Fujio Ito , Hiromichi Suzuki
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/06 , H01L23/49513 , H01L23/49531 , H01L23/49541 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/29007 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48257 , H01L2224/48599 , H01L2224/48639 , H01L2224/4911 , H01L2224/49171 , H01L2224/49175 , H01L2224/49431 , H01L2224/49433 , H01L2224/73265 , H01L2224/85399 , H01L2224/85439 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/07802 , H01L2924/10162 , H01L2924/10253 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/19107 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2924/3512 , H01L2924/00012
摘要： The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar (21d) irrespective of the inner lead (21b) pitch, by making the pitch of the pad (22a) smaller than the pitch of the inner lead (21b), or by forming the pad (22a) in a zigzag arrangement.
摘要翻译：本发明可以通过对半导体芯片（22）内部的每个电路部分的汇流条（21d）进行分离和连接来为每个电路部分供电，并且还可以增加用于功率的焊盘（22a）的数量提供或可以使用通常用于信号电源的引线（21a），通过进一步充分利用能够连接到母线（21d）而不考虑内部引线（21b）间距的特性，通过制造衬垫（22a）的间距小于内引线（21b）的间距，或通过以锯齿形布置形成焊盘（22a）。

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