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61. 发明申请

US20020089887A1 Built-in self-test arrangement for integrated circuit memory devices 有权
标题翻译：用于集成电路存储器件的内置自检布置
公开(公告)号：US20020089887A1
公开(公告)日：2002-07-11
申请号：US10023308
申请日：2001-12-17
发明人： Kuong Hua Hii , Danny R. Cline , Theo J. Powell
IPC分类号： G11C007/00
CPC分类号： G01R31/30 , G06F1/08 , G06F11/27 , G06F2201/88 , G11C5/147 , G11C11/401 , G11C29/12015 , G11C29/14 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/46 , G11C29/50 , G11C29/56012 , G11C2029/0407
摘要： An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
摘要翻译：集成电路具有内置的自检（BIST）布置（60）。内置的自检装置包括存储测试算法指令的只读存储器（ROM）（140）。 ROM逻辑电路（410）接收从只读存储器读取的指令，并根据该指令产生一组输出信号。 BIST寄存器420接收并存储用于控制集成电路的自检的逻辑电路的输出信号组。

62. 发明授权

US5604713A Circuitry and method that allows for external control of a data security device 失效
标题翻译：允许对数据安全设备进行外部控制的电路和方法
公开(公告)号：US5604713A
公开(公告)日：1997-02-18
申请号：US575209
申请日：1995-12-19
申请人： Timothy A. Short , Matthew H. Childs
发明人： Timothy A. Short , Matthew H. Childs
IPC分类号： G11C13/00
CPC分类号： G11C29/56012 , G06F21/74 , G11C29/50 , G11C7/24 , G11C2029/5602
摘要： A data security device is unitarily formed in an integrated circuit. A processor of the data security device operates in response to a clock signal provided at a clock input of the processor. Clock signal generation circuitry generates an internal clock signal. First processor-readable program code is configured to cause the processor to detect an internal, protectable, non-volatile indication of a state of the integrated circuit data security device. For example, one indication may be that non-volatile memory of the data security device has never been initialized. Another indication may be that the non-volatile memory of the data security device contains a manufacturing test pattern. Clock signal selection circuitry selectively provides a path for either the internal clock signal to be provided to the clock input of the processor or, alternatively, for an externally-provided clock signal to be provided to the clock input of the processor. Second processor-readable program code is configured to cause the processor to control the selection by the clock signal selection circuitry responsive to the state indication.
摘要翻译：数据安全装置在集成电路中整体形成。数据安全装置的处理器响应在处理器的时钟输入处提供的时钟信号而工作。时钟信号产生电路产生内部时钟信号。第一处理器可读程序代码被配置为使处理器检测集成电路数据安全设备的状态的内部的，可保护的，非易失性的指示。例如，一个指示可能是数据安全设备的非易失性存储器从未被初始化。另一个指示可能是数据安全设备的非易失性存储器包含制造测试模式。时钟信号选择电路选择性地提供用于将内部时钟信号提供给处理器的时钟输入的路径，或者替代地，外部提供的时钟信号被提供给处理器的时钟输入。第二处理器可读程序代码被配置为使处理器响应于状态指示由时钟信号选择电路控制选择。

63. 发明公开

US20240304274A1 ELECTRONIC DEVICE INCLUDING DRAM AND METHOD FOR OPERATING THE SAME 审中-公开
公开(公告)号：US20240304274A1
公开(公告)日：2024-09-12
申请号：US18596951
申请日：2024-03-06
申请人： Samsung Electronics Co., Ltd.
发明人： Jiyong YOO , Eunjoon KIM , Heesung LEE , Soonyeol HWANG
IPC分类号： G11C29/56
CPC分类号： G11C29/56016 , G11C29/56008 , G11C29/56012 , G11C2029/5604
摘要： An electronic device is provided. The electronic device includes dynamic random access memory (DRAM), memory, and one or more processors communicatively coupled to the DRAM and the memory, wherein the memory store one or more computer programs including computer-executable instructions that, when executed by the one or more processors, cause the electronic device to generate a first eye diagram based on training the DRAM with a driving voltage, identify a first parameter in a designated format corresponding to the generated first eye diagram, generate a second eye diagram based on training the DRAM with the driving voltage, compare the identified first parameter with a second parameter in the designated format corresponding to the generated second eye diagram, and adjust the driving voltage based on a result of the comparison between the first parameter and the second parameter.

64. 发明授权

US12032018B2 System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controller 有权
公开(公告)号：US12032018B2
公开(公告)日：2024-07-09
申请号：US18298305
申请日：2023-04-10
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Gang Zhao , Howard David , Xusheng Liu , Yongyao Li
IPC分类号： G06F11/00 , G01R31/317 , G11C29/02 , G11C29/56
CPC分类号： G01R31/3171 , G01R31/31709 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/56008 , G11C29/56012 , G11C2029/5602
摘要： A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

65. 发明公开

US20240055068A1 SIGNAL SKEW CORRECTION IN INTEGRATED CIRCUIT MEMORY DEVICES 审中-公开
公开(公告)号：US20240055068A1
公开(公告)日：2024-02-15
申请号：US18266782
申请日：2021-12-08
申请人： Rambus Inc.
发明人： Srinivas Satish Babu Bamdhamravuri , Panduka Wijetunga
IPC分类号： G11C29/50 , G11C29/56
CPC分类号： G11C29/50012 , G11C29/56012 , G11C29/56004 , G11C2029/5602
摘要： Technologies for signal skew correction in integrated circuit memory devices are described. An integrated circuit memory device includes a first interface to receive command/address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of CA signals and the clock signal and the data interface outputs the pattern of CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representative of a timing offset between the clock signal and a sampling point for the first interface.

66. 发明公开

US20230324457A1 System and Method for Receiver Equalization and Stressed Eye Testing Methodology for DDR5 Memory Controller 审中-公开
公开(公告)号：US20230324457A1
公开(公告)日：2023-10-12
申请号：US18298305
申请日：2023-04-10
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Gang Zhao , Howard David , Xusheng Liu , Yongyao Li
IPC分类号： G01R31/317 , G11C29/02 , G11C29/56
CPC分类号： G01R31/3171 , G11C29/022 , G11C29/023 , G11C29/56008 , G11C29/56012 , G01R31/31709 , G11C29/028 , G11C2029/5602
摘要： A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.

67. 发明授权

US10622036B2 Semiconductor system 有权
公开(公告)号：US10622036B2
公开(公告)日：2020-04-14
申请号：US16169746
申请日：2018-10-24
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： G11C7/10 , H04L7/00 , G06F13/16 , G11C7/22 , G11C29/56
CPC分类号： G11C7/1066 , G06F13/1689 , G11C7/222 , G11C29/56012 , H04L7/0008 , H04L7/0037 , G11C2207/2254
摘要： A semiconductor system includes a first semiconductor device configured to output a clock signal, a strobe signal and mode information signals, and detect a phase difference of the clock signal and the strobe signal depending on a detection signal. The semiconductor system may include a second semiconductor device configured to generate the detection signal by comparing phases of the clock signal and the strobe signal.

68. 发明申请

US20180313888A1 METHOD FOR CONTINUOUS TESTER OPERATION DURING MULTIPLE STAGE TEMPERATURE TESTING 审中-公开
公开(公告)号：US20180313888A1
公开(公告)日：2018-11-01
申请号：US15569255
申请日：2017-08-02
申请人： CELERINT, LLC
发明人： Howard H. ROBERTS, Jr.
IPC分类号： G01R31/26 , H01L21/687 , G01R1/04 , G01R31/28
CPC分类号： G01R31/2601 , G01R1/0458 , G01R31/2837 , G01R31/2849 , G01R31/2867 , G01R31/287 , G01R31/2874 , G01R31/2882 , G11C29/56008 , G11C29/56012 , G11C29/56016 , G11C2029/5002 , H01L21/68707
摘要： A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.

69. 发明授权

US10083761B2 Semiconductor device including chips capable of comparing data 有权
公开(公告)号：US10083761B2
公开(公告)日：2018-09-25
申请号：US15181495
申请日：2016-06-14
申请人： SK hynix Inc.
发明人： Min Chang Kim , Chang Hyun Kim , Do Yun Lee , Jae Jin Lee , Hun Sam Jung
IPC分类号： G11C29/38 , G11C7/22 , G11C7/10 , G11C29/26 , G11C29/40
CPC分类号： G11C29/38 , G11C7/10 , G11C7/1051 , G11C7/1063 , G11C7/22 , G11C29/46 , G11C29/56012 , G11C2029/2602 , G11C2029/4002 , G11C2029/5602
摘要： A semiconductor memory apparatus includes an input/output pad, a first data input/output circuit, a first data transfer circuit, a second data transfer circuit, and a test data comparison circuit. The input/output pad may be coupled to an external equipment. The first data input/output circuit may be coupled to the input/output pad. The first data transfer circuit may transfer data output from the first data input/output circuit to a first data storage region in response to a test write signal and transfer data output from the first data storage region to the first data input/output circuit in response to a test read signal. The second data transfer circuit may transfer data output from the first data input/output circuit to a second data storage region in response to the test write signal and transfer data output from the second data storage region to a second data input/output circuit in response to the test read signal. The test data comparison circuit may generate a test result signal by comparing data output from the first data storage region, the second data storage region, the first data transfer circuit, and the second data transfer circuit and output the test result signal to the external equipment through the input/output pad.

70. 发明申请

US20180269864A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180269864A1
公开(公告)日：2018-09-20
申请号：US15986367
申请日：2018-05-22
申请人： FUJI ELECTRIC CO., LTD.
发明人： Masashi AKAHANE
IPC分类号： H03K17/082 , G11C16/04 , G11C16/12 , G11C16/32 , G11C29/50 , G11C16/26
CPC分类号： H03K17/0828 , G11C16/0408 , G11C16/10 , G11C16/12 , G11C16/26 , G11C16/32 , G11C29/021 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56012 , G11C2029/5002 , G11C2029/5004 , G11C2029/5602 , H03K2017/0806
摘要： A semiconductor device including a first control circuit, a memory and a second control circuit. The first control circuit includes a monitoring section which receives a voltage signal which includes a pulse signal having a plurality of different voltage levels superimposed on a power source voltage, monitors a level of the voltage signal and outputs a monitoring result, and a regulator which generates an internal voltage. The memory receives the internal voltage. The second control circuit receives the internal voltage, reproduces a clock and data from the pulse signal on the basis of the monitoring result, and performs trimming on the memory using the clock and the data.

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