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1. 发明授权

US5677891A Circuitry and method that allows for external control of a data security device 失效
公开(公告)号：US5677891A
公开(公告)日：1997-10-14
申请号：US756565
申请日：1996-11-26
申请人： Timothy A. Short , Matthew H. Childs
发明人： Timothy A. Short , Matthew H. Childs
IPC分类号： G11C13/00
CPC分类号： G11C29/56012 , G06F21/74 , G11C29/50 , G11C7/24 , G11C2029/5602
摘要： A data security device is unitarily formed in an integrated circuit. A processor of the data security device operates in response to a clock signal provided at a clock input of the processor. Clock signal generation circuitry generates an internal clock signal. First processor-readable program code is configured to cause the processor to detect an internal, protectable, non-volatile indication of a state of the integrated circuit data security device. For example, one indication may be that non-volatile memory of the data security device has never been initialized. Another indication may be that the non-volatile memory of the data security device contains a manufacturing test pattern. Clock signal selection circuitry selectively provides a path for either the internal clock signal to be provided to the clock input of the processor or, alternatively, for an externally-provided clock signal to be provided to the clock input of the processor. Second processor-readable program code is configured to cause the processor to control the selection by the clock signal selection circuitry responsive to the state indication.

2. 发明授权

US5604713A Circuitry and method that allows for external control of a data security device 失效
标题翻译：允许对数据安全设备进行外部控制的电路和方法
公开(公告)号：US5604713A
公开(公告)日：1997-02-18
申请号：US575209
申请日：1995-12-19
申请人： Timothy A. Short , Matthew H. Childs
发明人： Timothy A. Short , Matthew H. Childs
IPC分类号： G11C13/00
CPC分类号： G11C29/56012 , G06F21/74 , G11C29/50 , G11C7/24 , G11C2029/5602
摘要： A data security device is unitarily formed in an integrated circuit. A processor of the data security device operates in response to a clock signal provided at a clock input of the processor. Clock signal generation circuitry generates an internal clock signal. First processor-readable program code is configured to cause the processor to detect an internal, protectable, non-volatile indication of a state of the integrated circuit data security device. For example, one indication may be that non-volatile memory of the data security device has never been initialized. Another indication may be that the non-volatile memory of the data security device contains a manufacturing test pattern. Clock signal selection circuitry selectively provides a path for either the internal clock signal to be provided to the clock input of the processor or, alternatively, for an externally-provided clock signal to be provided to the clock input of the processor. Second processor-readable program code is configured to cause the processor to control the selection by the clock signal selection circuitry responsive to the state indication.
摘要翻译：数据安全装置在集成电路中整体形成。数据安全装置的处理器响应在处理器的时钟输入处提供的时钟信号而工作。时钟信号产生电路产生内部时钟信号。第一处理器可读程序代码被配置为使处理器检测集成电路数据安全设备的状态的内部的，可保护的，非易失性的指示。例如，一个指示可能是数据安全设备的非易失性存储器从未被初始化。另一个指示可能是数据安全设备的非易失性存储器包含制造测试模式。时钟信号选择电路选择性地提供用于将内部时钟信号提供给处理器的时钟输入的路径，或者替代地，外部提供的时钟信号被提供给处理器的时钟输入。第二处理器可读程序代码被配置为使处理器响应于状态指示由时钟信号选择电路控制选择。

3. 发明授权

US5623545A Automatic data generation for self-test of cryptographic hash algorithms in personal security devices 失效
标题翻译：自动数据生成用于个人安全设备中加密散列算法的自检
公开(公告)号：US5623545A
公开(公告)日：1997-04-22
申请号：US521794
申请日：1995-08-31
申请人： Matthew H. Childs , Thomas M. Norcross
发明人： Matthew H. Childs , Thomas M. Norcross
IPC分类号： H04L9/32 , H04K1/00 , H04L9/28
CPC分类号： H04L9/0643 , H04L2209/125 , H04L2209/26
摘要： According to the present invention, the solution includes the hardware hash algorithm block to automatically generate data to hash from its initialization values and to run unassisted instead of needing a continuous supply of additional input data. This approach according to the present invention solves the above shortcomings of related solutions by eliminating the need to continuously feed input data to be hashed to obtain a high fault coverage. This reduces the sizes of the firmware and test vectors necessary to test the hardware. Also, since the hardware autonomously generates new data to hash, other hardware modules can be tested in parallel. This reduces the overall test time and cost. To remove the requirement of inputting multiple fixed length sub-blocks, additional sub-blocks are created from the initial sub-block using a hardware expansion function, and the hardware continues to run unattended for some predetermined number of sub-blocks. The hash hardware can use the expansion function, W[i]=W[i-3] xor W[i-8] xor W[i-14] xor W[i-16], to expand existing data into new data, where W[i-x] originates from the initial sub-block. By utilizing the non-linear xor function, W[i] will be random data if any of W[i-3], W[i-8], W[i-14], or W[i-16] are random. This expansion function is good for achieving high fault coverage because the new W values will likely be different from the other W values that have been hashed. This expansion function is convenient to use because it is utilized by the Secure Hash Algorithm as specified by the Secure Hash Standard FIPS PUB 180 and FIPS PUB 180-1 (includes a left rotate by one bit position).
摘要翻译：根据本发明，该解决方案包括硬件散列算法块，以从其初始化值自动生成数据进行散列，并且无需运行而不需要连续提供附加的输入数据。根据本发明的这种方法通过消除对连续馈送要散列的输入数据以获得高故障覆盖的需要来解决上述相关解决方案的缺点。这减少了测试硬件所需的固件和测试向量的大小。此外，由于硬件自主地生成新的散列数据，因此可以并行测试其他硬件模块。这降低了整体测试时间和成本。为了消除输入多个固定长度子块的要求，使用硬件扩展功能从初始子块创建附加子块，并且在某些预定数量的子块上，硬件继续无人值守运行。散列硬件可以使用扩展函数W [i] = W [i-3] xor W [i-8] xor W [i-14] xor W [i-16]将现有数据扩展为新数据，其中W [ix]来源于初始子块。通过利用非线性xor函数，如果W [i-3]，W [i-8]，W [i-14]或W [i-16]中的任一个是随机的，W [i]将是随机数据。这种扩展功能对于实现高故障覆盖是有好处的，因为新的W值可能与已经散列的其他W值不同。这种扩展功能便于使用，因为它由安全散列标准FIPS PUB 180和FIPS PUB 180-1（包括左旋转一位位置）所指定的安全散列算法所使用。

4. 发明授权

US5621337A Iterative logic circuit 失效
标题翻译：迭代逻辑电路
公开(公告)号：US5621337A
公开(公告)日：1997-04-15
申请号：US521348
申请日：1995-08-30
申请人： Matthew H. Childs
发明人： Matthew H. Childs
IPC分类号： G06F7/00 , H03K19/00 , H03K19/173
CPC分类号： G06F7/00
摘要： An iterative logic circuit for iteratively performing a logic function includes a two-input logic gate and a D-type flip-flop. The flip-flop receives and time-delays the output signal from the logic gate to provide a feedback signal as one of the input signals to the logic gate. By sequentially processing the feedback signal together with a serial input data signal, the logic gate iteratively performs an associative logic function (e.g. EXCLUSIVE-OR) upon the serial input data signal, thereby performing a parallel logic function by executing a serial logic operation.
摘要翻译：用于迭代执行逻辑功能的迭代逻辑电路包括双输入逻辑门和D型触发器。触发器接收来自逻辑门的输出信号的时间延迟，以将反馈信号提供给逻辑门的输入信号之一。通过顺序处理反馈信号和串行输入数据信号，逻辑门在串行输入数据信号上迭代地执行关联逻辑功能（例如，EXCLUSIVE-OR），从而通过执行串行逻辑运算来执行并行逻辑功能。

5. 发明授权

US5623648A Controller for initiating insertion of wait states on a signal bus 失效
标题翻译：控制器用于启动在信号总线上插入等待状态
公开(公告)号：US5623648A
公开(公告)日：1997-04-22
申请号：US521212
申请日：1995-08-30
申请人： Matthew H. Childs
发明人： Matthew H. Childs
IPC分类号： G06F13/42 , G06F1/04
CPC分类号： G06F13/4217
摘要： A controller for initiating an insertion of one or more wait states on a signal bus includes registers, AND logic circuits, a counter and a OR logic circuit. One register is for connecting to a signal bus and receiving therefrom a clock signal and in response thereto receiving and latching an address strobe signal to provide a latched address strobe signal. One AND logic circuit is for receiving the latched address strobe signal, connecting to the signal bus and receiving therefrom an address write signal and a chip select signal and logically. ANDing the latched address strobe signal, the address write signal and the chip select signal to provide a first ANDed signal. Another register is for receiving a second clock signal and in response thereto receiving and latching the first ANDed signal to provide a first latched ANDed signal. Another AND logic circuit is for receiving and logically ANDing the first latched ANDed signal and a decoded address signal to provide a second ANDed signal. The counter is for receiving the second ANDed signal and the second lock signal and in response thereto providing a multiple-bit count signal. The OR logic circuit is for receiving and logically ORing the first latched ANDed signal and the multiple-bit count signal to provide a wait state control signal for initiating an insertion of one or more wait states on the signal bus.
摘要翻译：用于启动在信号总线上插入一个或多个等待状态的控制器包括寄存器AND逻辑电路，计数器和OR逻辑电路。一个寄存器用于连接到信号总线并从其接收时钟信号，并响应于此来接收和锁存地址选通信号以提供锁存的地址选通信号。一个AND逻辑电路用于接收锁存的地址选通信号，连接到信号总线并从其接收地址写信号和片选信号并在逻辑上接收。对锁存的地址选通信号，地址写入信号和芯片选择信号进行调试，以提供第一个“与”信号。另一个寄存器用于接收第二时钟信号，响应于此，接收和锁存第一“与”信号以提供第一锁存的“与”信号。另一AND逻辑电路用于接收和逻辑地对第一锁存的与时信号和解码的地址信号进行逻辑“和”，以提供第二个“与”信号。该计数器用于接收第二个“与”信号和第二个锁定信号，并响应于此提供一个多位计数信号。 OR逻辑电路用于接收和逻辑地对第一锁存的与信号和多位计数信号进行逻辑或运算，以提供等待状态控制信号，以在信号总线上启动一个或多个等待状态的插入。

6. 发明授权

US5510741A Reset and clock circuit for providing valid power up reset signal prior to distribution of clock signal 失效
标题翻译：复位和时钟电路，用于在分配时钟信号之前提供有效的上电复位信号
公开(公告)号：US5510741A
公开(公告)日：1996-04-23
申请号：US521213
申请日：1995-08-30
申请人： Matthew H. Childs
发明人： Matthew H. Childs
IPC分类号： H03K17/22 , H03K3/02
CPC分类号： H03K17/22
摘要： A reset and clock circuit for providing a valid power-up reset signal prior to distribution of a clock signal includes power sensing circuitry, a clock generator and a reset generator. The power sensing circuitry monitors the power supply voltage and generates a power-up signal which is asserted when it has risen above a predetermined value. The power sensing circuitry also receives a clock signal and, in accordance with the power-up and clock signals, provides a number of power status signals. One of the power status signals is asserted in response to assertion of the power-up signal, while another is asserted in response to reception of a group of clock signal pulses. The clock generator, in response to assertion of the first power status signal, provides the clock signal. The reset generator, in accordance with the power status signals and clock signal, provides a number of reset signals each one of which is initially asserted prior to the providing of the clock signal by the clock signal generator. One of the reset signals is de-asserted in response to reception of another group of clock signal pulses, while another is de-asserted in response to reception of still another group of clock signal pulses.
摘要翻译：在分配时钟信号之前提供有效上电复位信号的复位和时钟电路包括功率检测电路，时钟发生器和复位发生器。功率感测电路监视电源电压并产生上电信号，该信号在其上升到高于预定值时被断言。功率感测电路还接收时钟信号，并且根据上电和时钟信号，提供多个电源状态信号。功率状态信号之一响应于上电信号的断言而被断言，而另一个功率状态信号响应于接收到一组时钟信号脉冲被断言。响应于第一电源状态信号的断言，时钟发生器提供时钟信号。根据功率状态信号和时钟信号，复位发生器提供多个复位信号，每个复位信号在由时钟信号发生器提供时钟信号之前被初始断言。响应于另一组时钟信号脉冲的接收，其中一个复位信号被解除断言，而另一个复位信号响应于另一组时钟信号脉冲的接收被解除断言。

7. 发明授权

US5608798A Crytographic device with secure testing function 失效
标题翻译：具有安全测试功能的凝视设备
公开(公告)号：US5608798A
公开(公告)日：1997-03-04
申请号：US520917
申请日：1995-08-30
申请人： Thomas H. Likens , Matthew H. Childs
发明人： Thomas H. Likens , Matthew H. Childs
IPC分类号： H04L9/00 , H04K1/00
CPC分类号： H04L9/0662 , H04L2209/26
摘要： A method of securely testing a cryptographic device need not be carried out in a secure testing facility by cleared personnel. First, a test cycle total count number is provided. Then, for each of a plurality of test cycles, the number being determined from the test cycle total count number, an input data signal is provided to the cryptographic device. The input data signal is encrypted to determine an encrypted signal, and the encrypted signal is then decrypted to determine a decrypted signal. Finally, the input data signal is compared to the decrypted signal. A cryptographic device includes receiving circuitry for receiving the input data signal and encryption circuitry that encrypts the input data signal to determine the encrypted signal. Decryption circuitry decrypts the encrypted signal to determine a decrypted signal, and comparing circuitry compares the input data signal to the decrypted signal. Finally, sequencing circuitry causes a plurality of input data signals to he sequentially provided to the receiving circuitry during a plurality of test cycles, one input data signal per test cycle.
摘要翻译：安全测试加密设备的方法不需要在被清理的人员的安全测试设施中进行。首先，提供测试周期总计数。然后，对于多个测试周期中的每一个，从测试周期总计数确定的数量，输入数据信号被提供给密码装置。输入数据信号被加密以确定加密信号，然后将加密的信号解密以确定解密的信号。最后，将输入数据信号与解密信号进行比较。密码装置包括用于接收输入数据信号的接收电路和加密输入数据信号以确定加密信号的加密电路。解密电路解密加密信号以确定解密信号，并且比较电路将输入数据信号与解密信号进行比较。最后，排序电路使得多个输入数据信号在多个测试周期期间依次提供给接收电路，每个测试周期一个输入数据信号。

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