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61. 发明授权

US07961496B2 Resistive memory cells and devices having asymmetrical contacts 有权
标题翻译：具有不对称触点的电阻式存储单元和器件
公开(公告)号：US07961496B2
公开(公告)日：2011-06-14
申请号：US12612187
申请日：2009-11-04
申请人： In-Gyu Baek , Moon-Sook Lee , Dong-Chul Kim
发明人： In-Gyu Baek , Moon-Sook Lee , Dong-Chul Kim
IPC分类号： G11C11/00
CPC分类号： H01L45/04 , G11C11/161 , G11C11/1659 , G11C13/0007 , G11C2213/52 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/1233 , H01L45/146 , H01L45/147
摘要： A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.
摘要翻译：存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

62. 发明授权

US07884699B2 Variable resistor element, manufacturing method thereof, and memory device provided with it 有权
标题翻译：可变电阻元件及其制造方法以及设置有该电阻元件的存储器件
公开(公告)号：US07884699B2
公开(公告)日：2011-02-08
申请号：US11997184
申请日：2006-07-21
申请人： Yasunari Hosoi
发明人： Yasunari Hosoi
IPC分类号： H01C7/10
CPC分类号： H01L45/04 , G11C13/0007 , G11C13/0026 , G11C2213/52 , G11C2213/79 , H01L27/2436 , H01L45/1233 , H01L45/145 , H01L45/1633 , H01L45/1675 , Y10T29/49082
摘要： A variable resistor element comprising a first electrode, a second electrode, and a variable resistor positioned between the first and second electrodes, and changing in electric resistance when a voltage pulse is applied between the both electrodes, has posed problems that it has a restriction of having to use noble metal electrodes as an electrode material and is not compatible with a conventional CMOS process. A variable resistor element using an oxynitride of transition metal element as a variable resistor exhibits a stable switching operation, is satisfactory in data retaining characteristics, and requires a small programming current. Since it does not necessarily require noble metal as an electrode material, it is high in compatibility with the existing CMOS process and easy to produce. It can be formed by a simple step of forming a variable resistor material into a film by oxidizing a lower electrode surface consisting of conductive nitride.
摘要翻译：一种可变电阻器元件，包括位于第一和第二电极之间的第一电极，第二电极和可变电阻器，以及当在两个电极之间施加电压脉冲时电阻变化的问题，其具有限制必须使用贵金属电极作为电极材料，并且与常规CMOS工艺不兼容。使用过渡金属元素的氧氮化物作为可变电阻器的可变电阻器元件具有稳定的开关操作，在数据保持特性方面是令人满意的，并且需要小的编程电流。由于不需要贵金属作为电极材料，因此与现有的CMOS工艺的兼容性高，易于制造。可以通过通过氧化由导电氮化物组成的下电极表面来形成可变电阻器材料到膜中的简单步骤来形成。

63. 发明授权

US07835177B2 Phase change memory cell and method of fabricating 有权
标题翻译：相变存储单元及其制造方法
公开(公告)号：US07835177B2
公开(公告)日：2010-11-16
申请号：US11493595
申请日：2006-07-27
申请人： Hong-Hui Hsu , Chien-Min Lee , Wen-Han Wang , Min-Hung Lee , Te-Sheng Chao , Yen Chuo , Yi-Chan Chen , Wei-Su Chen
发明人： Hong-Hui Hsu , Chien-Min Lee , Wen-Han Wang , Min-Hung Lee , Te-Sheng Chao , Yen Chuo , Yi-Chan Chen , Wei-Su Chen
IPC分类号： G11C11/00
CPC分类号： H01L45/1675 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A phase change memory (PCM) cell fabricated by etching a tapered structure into a phase change layer, and planarizing a dielectric layer on the phase change layer until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced, thereby lowering the operation current.
摘要翻译：通过将锥形结构蚀刻成相变层而制造的相变存储器（PCM）单元，并且平坦化相变层上的电介质层直到锥形结构的尖端暴露以接触加热电极。因此，相变层的露出端的面积被控制为极小的尺寸，相变层和加热电极之间的接触面积减小，从而降低了工作电流。

64. 发明授权

US07791925B2 Structures for resistive random access memory cells 有权
标题翻译：电阻随机存取存储单元的结构
公开(公告)号：US07791925B2
公开(公告)日：2010-09-07
申请号：US12262262
申请日：2008-10-31
申请人： Shaoping Li , Insik Jin , Zheng Gao , Eileen Yan , Kaizhong Gao , Haiwen Xi , Song Xue
发明人： Shaoping Li , Insik Jin , Zheng Gao , Eileen Yan , Kaizhong Gao , Haiwen Xi , Song Xue
IPC分类号： G11C7/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/32 , G11C2213/34 , G11C2213/52 , G11C2213/72 , H01L27/2436 , H01L45/04 , H01L45/122 , H01L45/146 , H01L45/147 , H01L45/1666
摘要： A resistive random access memory (RRAM) cell that includes a first electrode having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; a resistive layer having a lower portion, a continuous side portion and an upper portion, the lower portion and the continuous side portion having an outer surface and an inner surface; and a second electrode having a lower portion, an upper portion and an outer surface; wherein the outer surface of the resistive layer directly contacts the inner surface of the first electrode.
摘要翻译：一种电阻随机存取存储器（RRAM）单元，包括具有下部，连续侧部和上部的第一电极，所述下部和所述连续侧部具有外表面和内表面; 具有下部，连续侧部和上部的电阻层，所述下部和所述连续侧部具有外表面和内表面; 和具有下部，上部和外表面的第二电极; 其中电阻层的外表面直接接触第一电极的内表面。

65. 发明申请

US20100117069A1 OPTIMIZED ELECTRODES FOR RE-RAM 有权
标题翻译：优化的RE-RAM电极
公开(公告)号：US20100117069A1
公开(公告)日：2010-05-13
申请号：US12364732
申请日：2009-02-03
申请人： Depak C. Sekar , April Schricker , Xiying Chen , Klaus Schuegraf , Raghuveer S. Makala
发明人： Depak C. Sekar , April Schricker , Xiying Chen , Klaus Schuegraf , Raghuveer S. Makala
IPC分类号： H01L29/10 , H01L21/02 , H01L21/20 , H01L21/26
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/52 , H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1641 , H01L45/165
摘要： Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.
摘要翻译：公开了用于ReRAM存储单元的优化电极及其形成方法。一个方面包括形成第一电极，形成与第一电极接触的状态变化元件，处理状态变化元件，以及形成第二电极。处理状态改变元件增加了在第二电极和状态改变元件之间的界面处的势垒高度。另一方面包括以故意在第一电极中形成一定程度的非晶化的方式形成第一电极，形成与第一电极接触的状态改变元件。第一电极的非晶化程度至少与状态变化元件的非晶化程度一样大，或者比状态变化元件的非晶化程度小不超过5％。

66. 发明申请

US20100117053A1 METAL OXIDE MATERIALS AND ELECTRODES FOR RE-RAM 有权
标题翻译：用于RE-RAM的金属氧化物材料和电极
公开(公告)号：US20100117053A1
公开(公告)日：2010-05-13
申请号：US12364707
申请日：2009-02-03
申请人： Deepak C. Sekar , April Schricker
发明人： Deepak C. Sekar , April Schricker
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/52 , H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1641 , H01L45/165
摘要： Rewritable switching materials and methods for forming the same are described herein. One embodiment is a storage device comprising a first electrode, a state change element in contact with the first electrode, the state change element comprises ZrxYyOz, and a second electrode in contact with the state change element. A method for forming such a storage device is also disclosed herein. Another embodiment is a storage device comprising a first electrode a state change element in contact with the first electrode, the state change comprises at least one of cerium oxide or bismuth oxide, and a second electrode in contact with the state change element. A method for forming such a storage device is also disclosed herein.
摘要翻译：这里描述了可重写的开关材料及其形成方法。一个实施例是一种存储装置，包括第一电极，与第一电极接触的状态改变元件，状态改变元件包括Zr x Y y O z和与状态改变元件接触的第二电极。这里也公开了形成这种存储装置的方法。另一个实施例是一种存储装置，包括与第一电极接触的状态改变元件的第一电极，状态变化包括氧化铈或氧化铋中的至少一种以及与状态变化元件接触的第二电极。这里也公开了形成这种存储装置的方法。

67. 发明申请

US20100085142A1 VARIABLE RESISTOR ELEMENT, MANUFACTURING METHOD THEREOF, AND MEMORY DEVICE PROVIDED WITH IT 有权
标题翻译：可变电阻元件及其制造方法及其提供的存储器件
公开(公告)号：US20100085142A1
公开(公告)日：2010-04-08
申请号：US11997184
申请日：2006-07-21
申请人： Yasunari Hosoi
发明人： Yasunari Hosoi
IPC分类号： H01L27/10 , H01C17/00
CPC分类号： H01L45/04 , G11C13/0007 , G11C13/0026 , G11C2213/52 , G11C2213/79 , H01L27/2436 , H01L45/1233 , H01L45/145 , H01L45/1633 , H01L45/1675 , Y10T29/49082
摘要： A variable resistor element comprising a first electrode, a second electrode, and a variable resistor positioned between the first and second electrodes, and changing in electric resistance when a voltage pulse is applied between the both electrodes, has posed problems that it has a restriction of having to use noble metal electrodes as an electrode material and is not compatible with a conventional CMOS process. A variable resistor element using an oxynitride of transition metal element as a variable resistor exhibits a stable switching operation, is satisfactory in data retaining characteristics, and requires a small programming current. Since it does not necessarily require noble metal as an electrode material, it is high in compatibility with the existing CMOS process and easy to produce. It can be formed by a simple step of forming a variable resistor material into a film by oxidizing a lower electrode surface consisting of conductive nitride.
摘要翻译：一种可变电阻器元件，包括位于第一和第二电极之间的第一电极，第二电极和可变电阻器，以及当在两个电极之间施加电压脉冲时电阻变化的问题，其具有限制必须使用贵金属电极作为电极材料，并且与常规CMOS工艺不兼容。使用过渡金属元素的氧氮化物作为可变电阻器的可变电阻器元件具有稳定的开关操作，在数据保持特性方面是令人满意的，并且需要小的编程电流。由于不需要贵金属作为电极材料，因此与现有的CMOS工艺的兼容性高，易于制造。可以通过通过氧化由导电氮化物组成的下电极表面来形成可变电阻器材料到膜中的简单步骤来形成。

68. 发明申请

US20090103351A1 Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Memory Module 审中-公开
标题翻译：集成电路，制造集成电路的方法和存储器模块
公开(公告)号：US20090103351A1
公开(公告)日：2009-04-23
申请号：US11877558
申请日：2007-10-23
申请人： Cay-Uwe Pinnow , Wolfgang Raberg , Faiz Dahmani
发明人： Cay-Uwe Pinnow , Wolfgang Raberg , Faiz Dahmani
IPC分类号： G11C11/24 , H01G9/00
CPC分类号： H01G9/025 , G11C13/0011 , G11C2213/51 , G11C2213/52 , G11C2213/71 , H01G9/15 , H01L27/24 , H01L45/085 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： According to one embodiment of the present invention, an integrated circuit includes at least one memory device including: a reactive electrode layer, an inert electrode layer, and a solid electrolyte layer being disposed between the reactive electrode layer and the inert electrode layer; at least one interface layer being disposed between the solid electrolyte layer and the reactive electrode layer and/or between the solid electrolyte layer and the inert electrode layer. The material parameters of the at least one interface layer are chosen such that a crystallization of the solid electrolyte layer is at least partially suppressed.
摘要翻译：根据本发明的一个实施例，集成电路包括至少一个存储器件，包括：反应电极层，惰性电极层和固体电解质层，设置在反应电极层和惰性电极层之间; 至少一个界面层设置在固体电解质层和反应性电极层之间和/或固体电解质层和惰性电极层之间。选择至少一个界面层的材料参数，使得至少部分地抑制固体电解质层的结晶。

69. 发明授权

US07515454B2 CBRAM cell and CBRAM array, and method of operating thereof 失效
标题翻译： CBRAM单元和CBRAM阵列及其操作方法
公开(公告)号：US07515454B2
公开(公告)日：2009-04-07
申请号：US11497810
申请日：2006-08-02
申请人： Ralf Symanczyk
发明人： Ralf Symanczyk
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C13/003 , G11C11/5614 , G11C13/0011 , G11C2213/52 , G11C2213/78 , H01L27/24 , H01L45/085 , H01L45/1233
摘要： According to one embodiment of the present invention, a CBRAM cell includes a solid electrolyte block having at least three solid electrolyte contacting areas, electrodes electrically connected to the solid electrolyte contacting areas, wherein conductive paths are formable, erasable or detectable within the solid electrolyte block by applying voltages between the solid electrolyte contacting areas using the electrodes as voltage suppliers, and wherein the contacting areas are spatially separated from each other such that conductive paths starting from different solid electrolyte contacting areas or ending at different solid electrolyte contacting areas do not overlap each other.
摘要翻译：根据本发明的一个实施例，CBRAM单元包括固体电解质块，其具有至少三个固体电解质接触区域，电极与固体电解质接触区域电连接，其中导电路径可在固体电解质块内形成，可擦除或可检测通过使用电极作为电压供应商在固体电解质接触区域之间施加电压，并且其中接触区域在空间上彼此分离，使得从不同固体电解质接触区域开始或终止于不同固体电解质接触区域的导电路径不重叠其他。

70. 发明申请

US20080278990A1 RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS 有权
标题翻译：电阻开关非易失性存储器元件
公开(公告)号：US20080278990A1
公开(公告)日：2008-11-13
申请号：US12114667
申请日：2008-05-02
申请人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
发明人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
IPC分类号： G11C11/00 , H01L21/16
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
摘要翻译：提供具有电阻开关金属氧化物的非易失性存储元件。非易失性存储元件可以形成在集成电路上的一个或多个层中。每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。诸如二极管的电气设备可以与存储器元件串联耦合。第一导电层可以由金属氮化物形成。金属氧化物层可以包含与第一导电层相同的金属。金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。第一导电层，金属氧化物层和第二导电层可以包括子层。第二导电层可以包括粘合或阻挡层和功函数控制层。

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