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61. 发明授权

US4642797A High speed first-in-first-out memory 失效
标题翻译：高速先进先出存储器
公开(公告)号：US4642797A
公开(公告)日：1987-02-10
申请号：US551735
申请日：1983-11-10
申请人： Barry A. Hoberman
发明人： Barry A. Hoberman
IPC分类号： G06F5/06 , G06F5/16 , G11C7/00 , G11C13/00
CPC分类号： G06F5/16
摘要： A high speed M-stack fall-through FIFO memory system is disclosed which reduces fall-through delay and which permits at least a doubling of the maximum shift rates at input and output ports. Input port data may be entered in one of M physical memory locations and output port data may be read from one of M physical memory locations.
摘要翻译：公开了一种高速M堆栈落下FIFO存储器系统，其降低了落差延迟，并且允许在输入和输出端口处的最大偏移速率的至少加倍。输入端口数据可以输入到M个物理存储器位置之一中，并且输出端口数据可以从M个物理存储器位置中的一个读取。

62. 发明授权

US4433394A First-in first-out storage and processing unit making use thereof 失效
标题翻译：先进先出的存储和处理单元利用它
公开(公告)号：US4433394A
公开(公告)日：1984-02-21
申请号：US303186
申请日：1981-09-17
申请人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
发明人： Shunichi Torii , Shigeo Nagashima , Koichiro Omoda
IPC分类号： G06F3/06 , G06F5/06 , G06F5/16 , G06F12/00 , G06F12/06 , G06F17/16 , G11C7/00 , G11C19/00
CPC分类号： G06F5/16
摘要： A FIFO memory comprises a plurality of readable and writable data banks, a mode indicating circuit for indicating a write mode to a plurality of data banks repetitively, and a read/write control circuit for writing received data to the data bank to which the write mode has been indicated and reading the data from the data banks to which the write mode is not indicated.
摘要翻译： FIFO存储器包括多个可读写数据库，用于向多个数据组重复地指示写入模式的模式指示电路以及用于将接收的数据写入到写模式的数据组的读/写控制电路已经被指示并从未指示写入模式的数据库读取数据。

63. 发明授权

US4415994A Random access memory arrangements 失效
标题翻译：随机存取存储器布置
公开(公告)号：US4415994A
公开(公告)日：1983-11-15
申请号：US302107
申请日：1981-09-14
申请人： John G. S. Ive , Alan C. Thirlwall
发明人： John G. S. Ive , Alan C. Thirlwall
IPC分类号： H04N5/956 , G06F5/16 , G06F12/06 , G06F13/16 , G09G5/00 , G11B20/10 , G11C7/00 , G11C13/00
CPC分类号： G06F5/16 , G11C7/00
摘要： A random access memory arrangement for reading data out of and into a random access memory asynchronously, for example, to effect time base correction of a digital television signal, comprises a random access memory having common read and write data terminals, an input circuit for supplying input data to said read and write data terminals for writing in the random access memory, a first output latch circuit connected to the read and write data terminals, a second output latch circuit connected to the first latch circuit, and means for supplying control signals to enable the random access memory to write the input data therein at given addresses in synchronism with write pulses of a write pulse signal, to enable the random access memory to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, the read pulse signal being asynchronous with the write pulse signal, to control the first output latch circuit to hold and to supply to the second output latch circuit data supplied to the first latch circuit immediately prior to each write pulse, and to pass therethrough to the second latch circuit data supplied to the first latch circuit at all other times, and to control the second latch circuit to hold the data supplied to it by the first latch circuit immediately prior to the beginning of each read pulse until the beginning of the next succeeding read pulse and to supply the data so held to an output of the arrangement.
摘要翻译：一种随机存取存储装置，用于异步地将数据读出并进入随机存取存储器，例如实现数字电视信号的时基校正，包括具有公共读和写数据端的随机存取存储器，用于提供数据的输入电路将数据输入到所述读取和写入数据终端以写入随机存取存储器中，连接到读和写数据端的第一输出锁存电路，连接到第一锁存电路的第二输出锁存电路，以及用于将控制信号提供给使得随机存取存储器以与写入脉冲信号的写入脉冲同步地在给定的地址上写入输入数据，以使得随机存取存储器与读取脉冲信号的读取脉冲同步地从其中给定的地址读出输出数据，读取脉冲信号与写入脉冲信号异步，以控制第一输出锁存电路保持并提供给第二个o 在每个写入脉冲之前提供给第一锁存电路的输出锁存电路数据，并且在所有其他时间通过其提供给提供给第一锁存电路的第二锁存电路数据，并且控制第二锁存电路以保持所提供的数据由紧接在每个读取脉冲开始之前的第一锁存电路直到下一个后续读取脉冲的开始，并且将所保持的数据提供给该装置的输出。

64. 发明授权

US4333143A Input process sequence controller 失效
标题翻译：输入过程顺序控制器
公开(公告)号：US4333143A
公开(公告)日：1982-06-01
申请号：US95920
申请日：1979-11-19
申请人： Powell L. Calder
发明人： Powell L. Calder
IPC分类号： G06F5/16 , G06F13/12 , G06F13/28 , G06F3/00
CPC分类号： G06F5/16 , G06F13/124 , G06F13/28
摘要： An input process sequence controller provides a sophisticated communication processing link between a central processor and peripheral digital apparatus. Data is transmitted from the peripheral digital apparatus to the process sequence controller whose function is to process that incoming data as commanded, to relieve the central processor of that task. The process sequence controller has a processor unit, controlled by a Read-only Memory for performing certain functions on the incoming data. The incoming data is received by one portion of a first swapping buffer while a second portion transmits previously received data to the processor unit. When the second portion is emptied, it begins receiving data while the first portion transmits data. A first portion of a second swapping buffer receives processed data from the processor unit while a second portion transmits processed data to the central processor. When the second portion is emptied, it begins receiving processed data while the first portion transmits its processed data. This procedure continues during an operation.
摘要翻译：输入过程顺序控制器在中央处理器和外围数字设备之间提供复杂的通信处理链路。数据从外围数字设备发送到处理序列控制器，其功能是按照命令处理输入数据，以缓解中央处理器的任务。处理序列控制器具有由仅读存储器控制的处理器单元，用于对输入数据执行某些功能。输入数据由第一交换缓冲器的一部分接收，而第二部分将先前接收到的数据发送到处理器单元。当第二部分被清空时，它开始接收数据，而第一部分发送数据。第二交换缓冲器的第一部分从处理器单元接收经处理的数据，而第二部分将经处理的数据发送到中央处理器。当第二部分被清空时，它开始接收处理的数据，而第一部分发送其处理的数据。此过程在操作期间继续。

65. 发明申请

US20180341460A1 FIXED-POINT AND FLOATING-POINT ARITHMETIC OPERATOR CIRCUITS IN SPECIALIZED PROCESSING BLOCKS 审中-公开
公开(公告)号：US20180341460A1
公开(公告)日：2018-11-29
申请号：US16056173
申请日：2018-08-06
申请人： ALTERA CORPORATION
发明人： Martin Langhammer
IPC分类号： G06F7/485 , G06F7/505 , G06F5/01 , G06F5/16 , G06F7/483
CPC分类号： G06F7/485 , G06F5/012 , G06F5/16 , G06F7/483 , G06F7/505 , G06F2207/3824
摘要： The present embodiments relate to circuitry that efficiently performs floating-point arithmetic operations and fixed-point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. If desired, the specialized processing blocks may include configurable interconnect circuitry to support a variety of different use modes. For example, the specialized processing block may efficiently perform a fixed-point or floating-point addition operation or a portion thereof, a fixed-point or floating-point multiplication operation or a portion thereof, a fixed-point or floating-point multiply-add operation or a portion thereof, just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and perform together more complex operations such as a recursive mode dot product of two vectors of floating-point numbers or a Radix-2 Butterfly circuit, just to name a few.

66. 发明申请

US20170237678A1 WORK CONSERVING SCHEDULAR BASED ON RANKING 审中-公开
公开(公告)号：US20170237678A1
公开(公告)日：2017-08-17
申请号：US15582144
申请日：2017-04-28
申请人： Cisco Technology, Inc.
发明人： Sha Ma , Philip Chen
IPC分类号： H04L12/865 , H04L12/875 , G06F9/48 , H04L12/863
CPC分类号： H04L47/6275 , G06F5/16 , G06F9/4881 , G06F2205/064 , H04L45/74 , H04L47/50 , H04L47/562 , H04L47/62 , H04L47/623
摘要： A work conserving scheduler can be implemented based on a ranking system to provide the scalability of time stamps while avoiding the fast search associated with a traditional time stamp implementation. Each queue can be assigned a time stamp that is initially set to zero. The time stamp for a queue can be incremented each time a data packet from the queue is processed. To provide varying weights to the different queues, the time stamp for the queues can be incremented at varying rates. The data packets can be processed from the queues based on the tier rank order of the queues as determined from the time stamp associated with each queue. To increase the speed at which the ranking is determined, the ranking can be calculate from a subset of the bits defining the time stamp rather than the entire bit set.

67. 发明授权

US09684487B2 Line-multiplexed UART 有权
公开(公告)号：US09684487B2
公开(公告)日：2017-06-20
申请号：US14631078
申请日：2015-02-25
申请人： QUALCOMM Incorporated
发明人： Lalan Jee Mishra , Richard Dominic Wietfeldt , George Alan Wiley
IPC分类号： G06F13/00 , G06F5/16 , G06F13/40 , G06F13/16 , G06F1/12 , G06F5/06 , G06F13/38
CPC分类号： G06F5/16 , G06F1/12 , G06F5/065 , G06F13/1673 , G06F13/385 , G06F13/4022
摘要： A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.

68. 发明授权

US09652371B2 Lookahead scheme for prioritized reads 有权
公开(公告)号：US09652371B2
公开(公告)日：2017-05-16
申请号：US14624621
申请日：2015-02-18
申请人： Apple Inc.
发明人： Rajat Goel , Hari S. Kannan , Khurram Z. Malik
IPC分类号： G06F13/16 , G06F12/02 , G11C8/06 , G11C8/16 , G06F5/16 , G06F12/00
CPC分类号： G06F12/0215 , G06F5/16 , G06F13/1673 , G06F2212/301 , G11C8/06 , G11C8/16
摘要： A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

69. 发明授权

US09547473B2 Data processing 有权
标题翻译：数据处理
公开(公告)号：US09547473B2
公开(公告)日：2017-01-17
申请号：US14457367
申请日：2014-08-12
申请人： Sony Computer Entertainment Europe Limited
发明人： Neil Jonathan Brown , Phillip Rogers
IPC分类号： G06F13/28 , G06F13/12 , G06F13/38 , G06F5/16 , G06F1/16 , G06F9/44 , G06F3/06 , G06F9/46 , G06F9/48 , G06F13/32 , G09G5/39 , G06F11/14
CPC分类号： G06F5/16 , G06F1/1643 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F9/4418 , G06F9/461 , G06F9/4881 , G06F11/1438 , G06F11/1446 , G06F13/32 , G06F2003/0691 , G09G5/39
摘要： A data processing apparatus comprises a processor having an internal state dependent upon execution of application program code, the processor being configured to generate display data relating to images to be displayed and to buffer display data relating to a most recent period of execution of a currently executing application. The apparatus includes RAM for storing temporary data relating to a current operational state of program execution. The apparatus also includes a data transfer controller configured to transfer data from the RAM relating to the currently executing application, data relating to a current internal state of the processor and buffered display data to suspend data memory, and to transfer data from the suspend data memory to RAM and to the processor to recreate an execution state of an application at a time the suspend instruction was executed, and to retrieve display data relating to the resumed application.
摘要翻译：数据处理装置包括具有取决于应用程序代码的执行的内部状态的处理器，所述处理器被配置为生成与要显示的图像相关的显示数据，并且缓冲与当前执行的最近执行周期有关的显示数据应用。该装置包括用于存储与程序执行的当前操作状态有关的临时数据的RAM。该装置还包括：数据传送控制器，被配置为从与RAM相关的当前执行的应用程序传输数据，与处理器的当前内部状态有关的数据和缓冲的显示数据以暂停数据存储器，并且从挂起数据存储器传送数据到RAM和处理器，以在执行暂停指令时重新创建应用的执行状态，并且检索与恢复的应用有关的显示数据。

70. 发明申请

US20150312083A1 SELF TRACK SCHEME FOR MULTI FREQUENCY BAND SERIALIZER DE-SERIALIZER I/O CIRCUITS 有权
标题翻译：多频段串行编解码器I / O电路的自拍方案
公开(公告)号：US20150312083A1
公开(公告)日：2015-10-29
申请号：US14704694
申请日：2015-05-05
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： Sheau Jiung Lee , Mau-Chung Frank Chang , Yanghyo Kim
IPC分类号： H04L27/38 , G06F5/16 , G06F13/40 , H04L27/36
CPC分类号： H04L27/38 , G06F5/16 , G06F13/4059 , G06F13/4072 , G06F13/4278 , H04L27/364
摘要： A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.
摘要翻译：具有自我跟踪电路的串行器和解串器电路，其特别适用于将数字数据从一个集成电路（芯片）传送到另一个集成电路（芯片）到另一个用于实现芯片到芯片通信。这些电路是可扩展的并且利用多频调制机制（例如，QAM），用于将数字数据位转换成多个频率的串行模拟流，用于通过芯片I / O连接进行通信。在发射机侧产生的跟踪脉冲通过与数据相同的路径进行串行化，并通过解串器中相同的路径解调，以提供与数据的同步，而不需要复杂的基带处理。

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