专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US11768731B2 System and method for transparent register data error detection and correction via a communication bus 有权
公开(公告)号：US11768731B2
公开(公告)日：2023-09-26
申请号：US16402532
申请日：2019-05-03
申请人： Infineon Technologies AG
发明人： Heimo Hartlieb , Christian Heiling
IPC分类号： G06F11/10 , G06F13/42 , G06F13/16
CPC分类号： G06F11/1048 , G06F13/1605 , G06F13/4204 , G06F13/4282 , G06F2213/0002
摘要： A method includes detecting in a communication bus a write command to a first circuit and comparing a write address of the write command with a set of safe addresses. When the write address matches a safe address of the set of safe addresses, an error correction code (ECC) is generated based at least on write data of the write command, and the ECC is stored in a memory of a parameter safe storage circuit. A read command to the first circuit is detected in the communication bus, a read address of the read command is compared with the set of safe addresses, and, when the read address matches a safe address of the set of safe addresses, it is determined whether read data of the read command is corrupted based on the stored ECC, and an error notification is provided when the read data is determined to be corrupted.

62. 发明公开

US20230185754A1 PARALLEL-TO-SERIAL INTERFACE CIRCUIT AND TRANSMISSION DEVICE HAVING THE SAME 审中-公开
公开(公告)号：US20230185754A1
公开(公告)日：2023-06-15
申请号：US17899883
申请日：2022-08-31
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Eunseok SHIN , Woochul JUNG , Jungho KO , Myoungbo KWAK , Jaewoo PARK , Sunjae LIM , Junghwan CHOI
IPC分类号： G06F13/42 , H03M9/00
CPC分类号： G06F13/4204 , H03M9/00 , G06F13/4282 , H03K17/6871
摘要： A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

63. 发明申请

US20180314655A1 POWER-ORIENTED BUS ENCODING FOR DATA TRANSMISSION 审中-公开
公开(公告)号：US20180314655A1
公开(公告)日：2018-11-01
申请号：US15581516
申请日：2017-04-28
申请人： Advanced Micro Devices, Inc.
发明人： Greg Sadowski , Tri Minh Nguyen
IPC分类号： G06F13/16 , G06F13/40
CPC分类号： G06F13/1678 , G06F1/3253 , G06F13/4072 , G06F13/4204
摘要： Systems, apparatuses, and methods for reducing the toggle rates on buses are disclosed. A computing system includes a source which provides packets for transmission on a bus. The packet is compressed by a compression engine. The compressed data format of the packet includes locations (bit positions) referred to as holes which do not include valid data. A bus configuration module identifies the locations of the holes and replaces the holes with information from a previous packet transmitted earlier on the bus. The bus configuration module also determines a new transmission bus width for the packet for lowering the bus toggle rate on the bus during transmission.

64. 发明授权

US10037291B2 Semiconductor memory apparatus and data input/output method thereof 有权
公开(公告)号：US10037291B2
公开(公告)日：2018-07-31
申请号：US14713738
申请日：2015-05-15
申请人： SK hynix Inc.
发明人： Kie Bong Ku
IPC分类号： G11C7/00 , G06F13/16 , G06F13/42
CPC分类号： G06F13/1668 , G06F13/4204 , G06F13/4282 , G11C7/10 , G11C7/1006 , G11C7/1048
摘要： A semiconductor memory apparatus may include a write data bus inversion unit and a write data polarity change unit. The write data bus inversion unit may invert a level of an input data and may generate an inversion change data when a majority of the input data have a predetermined level. The write data polarity change unit may invert a level of the inversion change data based on a write signal and a first bank address signal and generate a polarity change data.

65. 发明申请

US20140223090A1 ACCESSING CONTROL REGISTERS OVER A DATA BUS 有权
标题翻译：数据总线上的访问控制寄存器
公开(公告)号：US20140223090A1
公开(公告)日：2014-08-07
申请号：US13757498
申请日：2013-02-01
申请人： APPLE INC
发明人： Michael Ross Malone
IPC分类号： G11C7/10 , G06F17/30 , G11C19/00
CPC分类号： G11C19/00 , G06F13/00 , G06F13/4204
摘要： An electronic apparatus that includes a controlled device with a plurality of control registers. A data bus is coupled between the controlled device and a processor, and an interface is configured to receive a plurality of portions of data read from or to be written to the plurality of control registers. The electronic apparatus also includes a correlation circuit configured to associate at least some of the plurality of portions of data with respective physical addresses of the plurality of control registers based on respective positions of the respective portions of data within the plurality.
摘要翻译：一种电子设备，包括具有多个控制寄存器的受控设备。数据总线耦合在受控设备和处理器之间，并且接口被配置为接收从多个控制寄存器读取或写入多个控制寄存器的多个数据部分。电子设备还包括相关电路，其被配置为基于多个控制寄存器中的多个部分中的至少一些数据与多个控制寄存器中的相应物理地址相关联，基于多个数据的相应部分的相应位置。

66. 发明授权

US08751709B2 Hybrid interface for serial and parallel communication 有权
标题翻译：用于串行和并行通信的混合接口
公开(公告)号：US08751709B2
公开(公告)日：2014-06-10
申请号：US13934147
申请日：2013-07-02
申请人： Silicon Image, Inc.
发明人： Alan T. Ruberg , Roger Isaac
IPC分类号： G06F13/12 , G06F13/20
CPC分类号： G06F13/4204 , G06F13/4045 , G06F13/4282 , H04L29/10 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.
摘要翻译：本发明的实施例一般涉及用于串行和并行通信的混合接口。一种方法的实施例包括初始化用于将数据传输到第二装置的数据或从第二装置接收数据的第一装置，将用于第一装置的接口切换到用于并行接口的第一模式，所述并行接口包括第一多个引脚，以及经由所述第一多个引脚在所述第一模式中发送或接收并行数据。该方法还包括将第一装置的接口切换到用于串行接口的第二模式，串行接口包括第二多个引脚，第一多个引脚和第二多个引脚都包括重叠的引脚组，以及通过第二多个引脚在第二模式中发送或接收串行数据。

67. 发明授权

US08677041B2 Balancing loads of a plurality of bus lanes of a snooping-based bus using a receiver, analyzer, and controller 失效
标题翻译：使用接收器，分析仪和控制器平衡基于窥探的总线的多个总线通道的负载
公开(公告)号：US08677041B2
公开(公告)日：2014-03-18
申请号：US13221051
申请日：2011-08-30
申请人： Andreas Christian Doering
发明人： Andreas Christian Doering
IPC分类号： G06F12/00
CPC分类号： G06F13/4204
摘要： A method and system for balancing loads of a plurality of bus lanes of a snooping-based bus. The system includes: a receiver for receiving snoop transactions from the bus lanes, each of the snoop transactions having a snoop request and at least one snoop response, an analyzer for analyzing respective actual and expected loads of each of the bus lanes dependent on the received snoop transactions, and a controller for providing a next snoop request from a number of outstanding snoop requests to a buffer allocated to the system, where the buffer is dependent on the analyzed loads of the bus lanes.
摘要翻译：一种用于平衡基于窥探的总线的多个总线通道的负载的方法和系统。该系统包括：用于从总线通道接收窥探事务的接收器，每个窥探事务具有窥探请求和至少一个侦听响应;分析器，用于分析取决于所接收到的每个总线通道的各个实际和预期负载监听事务，以及控制器，用于从分配给系统的缓冲区中提供来自多个未完成侦听请求的下一个窥探请求，其中缓冲区取决于分析的总线通道的负载。

68. 发明申请

US20130290581A1 HYBRID INTERFACE FOR SERIAL AND PARALLEL COMMUNICATION 有权
标题翻译：用于串行和并行通信的混合接口
公开(公告)号：US20130290581A1
公开(公告)日：2013-10-31
申请号：US13934147
申请日：2013-07-02
申请人： Silicon Image, Inc.
发明人： Alan T. Ruberg , Roger Isaac
IPC分类号： G06F13/42
CPC分类号： G06F13/4204 , G06F13/4045 , G06F13/4282 , H04L29/10 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.
摘要翻译：本发明的实施例一般涉及用于串行和并行通信的混合接口。一种方法的实施例包括初始化用于将数据传输到第二装置的数据或从第二装置接收数据的第一装置，将用于第一装置的接口切换到用于并行接口的第一模式，所述并行接口包括第一多个引脚，以及经由所述第一多个引脚在所述第一模式中发送或接收并行数据。该方法还包括将第一装置的接口切换到用于串行接口的第二模式，串行接口包括第二多个引脚，第一多个引脚和第二多个引脚都包括重叠的引脚组，以及通过第二多个引脚在第二模式中发送或接收串行数据。

69. 发明授权

US08510487B2 Hybrid interface for serial and parallel communication 有权
标题翻译：用于串行和并行通信的混合接口
公开(公告)号：US08510487B2
公开(公告)日：2013-08-13
申请号：US12704417
申请日：2010-02-11
申请人： Alan T. Ruberg , Roger D. Isaac
发明人： Alan T. Ruberg , Roger D. Isaac
IPC分类号： G06F13/12 , G06F13/36
CPC分类号： G06F13/4204 , G06F13/4045 , G06F13/4282 , H04L29/10 , Y02D10/14 , Y02D10/151
摘要： Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.
摘要翻译：本发明的实施例一般涉及用于串行和并行通信的混合接口。一种方法的实施例包括初始化用于将数据传输到第二装置的数据或从第二装置接收数据的第一装置，将用于第一装置的接口切换到用于并行接口的第一模式，所述并行接口包括第一多个引脚，以及经由所述第一多个引脚在所述第一模式中发送或接收并行数据。该方法还包括将第一装置的接口切换到用于串行接口的第二模式，串行接口包括第二多个引脚，第一多个引脚和第二多个引脚都包括重叠的引脚组，以及通过第二多个引脚在第二模式中发送或接收串行数据。

70. 发明申请

US20130188656A1 Communicating Control Information for a Data Communications Link Via a Line Being Calibrated 审中-公开
标题翻译：通过校准的线路通信数据通信链路的控制信息
公开(公告)号：US20130188656A1
公开(公告)日：2013-07-25
申请号：US13791877
申请日：2013-03-08
申请人： International Business Machines Corporation
发明人： Frank D. Ferraiolo , Robert J. Reese , Susan M. Eickhoff , Michael B. Spear
IPC分类号： H04J3/06
CPC分类号： H04J3/06 , G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： Control information for controlling a parallel data link is communicated on a line being calibrated. Preferably, the parallel data link includes a redundant line. The redundant line permits one line to be calibrated while the others carry functional data, a switching mechanism enabling each line to be selected in turn for calibration. The control information preferably includes information for coordinating calibration activity. Preferably, the link is bi-directional, having a separate redundant line in each direction, enabling a bi-directional handshaking protocol to be used for communicating control information. Preferably, the lines selected for calibration are time-multiplexed to carry calibration patterns and control information at different time intervals.
摘要翻译：用于控制并行数据链路的控制信息在被校准的线路上传送。优选地，并行数据链路包括冗余线路。冗余线路允许一行校准，而另一条线路进行功能数据，切换机制使每条线路依次被选择进行校准。控制信息优选地包括用于协调校准活动的信息。优选地，链路是双向的，在每个方向上具有单独的冗余线路，使得双向握手协议能够用于传送控制信息。优选地，选择用于校准的线被时间复用以在不同的时间间隔传送校准图案和控制信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式