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61. 发明授权

US06658553B1 Universal pointer implementation scheme for uniformly addressing distinct memory spaces in a processor's address space 有权
标题翻译：通用指针实现方案，用于统一处理处理器地址空间中的不同存储空间
公开(公告)号：US06658553B1
公开(公告)日：2003-12-02
申请号：US09548987
申请日：2000-04-14
申请人： Zhimin Ding , Gregory K. Goodhue , Ata R. Khan
发明人： Zhimin Ding , Gregory K. Goodhue , Ata R. Khan
IPC分类号： G06F1200
CPC分类号： G06F9/30043 , G06F9/342 , G06F12/0623
摘要： A processing system supports memory access based on distinct memory space access instructions as well as universal access instructions that are independent of memory space partitions. Conventional memory-space dependent instructions, such as MOV, MOVX, and MOVC, provide an optimized addressing scheme, and an extended memory-space independent instruction EMOV provides an optimized code efficiency, processing speed, and ease of code generation. A mapping between the discrete memory space partitions and a “universal” memory space allocation is provided. The processing hardware interprets the universal address to determine the corresponding memory space, and provides the access to an address within that memory space.
摘要翻译：处理系统支持基于不同存储器空间访问指令的存储器访问以及独立于存储器空间分区的通用访问指令。传统的与存储器空间相关的指令，例如MOV，MOVX和MOVC，提供了优化的寻址方案，扩展的存储空间独立指令EMOV提供了优化的代码效率，处理速度和代码生成的便利性。提供了离散存储器空间分区与“通用”存储器空间分配之间的映射。处理硬件解释通用地址以确定相应的存储器空间，并提供对该存储器空间内的地址的访问。

62. 发明授权

US06654646B2 Enhanced memory addressing control 有权
公开(公告)号：US06654646B2
公开(公告)日：2003-11-25
申请号：US09735967
申请日：2000-12-13
申请人： Thomas Earl Bowers , Robert Joseph Gamoke , Glen D. Rocque , Paul Ronald Wiley
发明人： Thomas Earl Bowers , Robert Joseph Gamoke , Glen D. Rocque , Paul Ronald Wiley
IPC分类号： G05B1918
CPC分类号： G06F9/342 , G06F9/3802 , G06F9/3824 , G06F12/0623
摘要： A processing or control system having arrangements for separately and simultaneously generating instruction addresses and data addresses having two bus systems for accessing instruction and data storage, and having a single address range for both instructions and data. The boundary between the instruction range and the data range can be varied and placed under the control of the processor according to the needs of the particular application being processed. Some or all of the blocks of storage can access either the instruction bus or the data bus system, and the selection is made under the control of a control register within the processor. Advantageously, applications which require a larger amount of instruction storage, this can be provided; for applications which require a larger amount of data storage, that can be provided also; both are limited only by the total amount of storage available.

63. 发明申请

US20030105915A1 Address correcting method and device for a simultaneous dynamic random access memory module 审中-公开
标题翻译：用于同时动态随机存取存储器模块的地址校正方法和装置
公开(公告)号：US20030105915A1
公开(公告)日：2003-06-05
申请号：US09996723
申请日：2001-11-30
发明人： Shin-Husiung Lien
IPC分类号： G06F012/00
CPC分类号： G06F12/0623
摘要： The present invention relates to an address correcting method and device for a simultaneous dynamic random access memory module using the nature of a column/row address to enable the computer to take the capacity of the simultaneous dynamic random access memory module as a higher capacity thereby to enhance the business value of the simultaneous dynamic random access memory module; in addition, by setting an address line of the simultaneous dynamic random access memory module as a specific value, such as 1 or 0, to make half of the undamaged and useable capacity of an undesirable simultaneous dynamic random access memory module be utilized efficiently thereby to reduce the undesired rate of the simultaneous dynamic random access memory module so as to enhance the usability of the simultaneous dynamic random access memory module with high industrial utilization.
摘要翻译：本发明涉及使用列/行地址的性质的同时动态随机存取存储器模块的地址校正方法和装置，以使得计算机能够将同时动态随机存取存储器模块的容量作为较高容量，从而提升同步动态随机存取存储器模块的业务价值; 此外，通过将同时动态随机存取存储器模块的地址线设置为诸如1或0的特定值，以使得不期望的同时动态随机存取存储器模块的未损坏和可用容量的一半被有效地利用，从而降低同步动态随机存取存储器模块的不需要的速率，从而提高高工业利用率的同时动态随机存取存储器模块的可用性。

64. 发明申请

US20020097434A1 Method and apparatus for performing multi-function and effectively managing memories 失效
标题翻译：用于执行多功能和有效管理存储器的方法和装置
公开(公告)号：US20020097434A1
公开(公告)日：2002-07-25
申请号：US09992948
申请日：2001-11-05
发明人： Yasunori Tsukioka
IPC分类号： G06F015/00 , B41B001/00
CPC分类号： G06F12/0623 , H04N1/00127 , H04N1/32358 , H04N2201/001 , H04N2201/0081 , H04N2201/0082 , H04N2201/0086 , H04N2201/0087 , H04N2201/3288 , H04N2201/3295 , H04N2201/3297
摘要： A multi-function apparatus includes a basic memory, a socket, and a controller. The basic memory includes at least a first image memory area for a copying function and a second image memory area for a facsimile function. The socket connects an add-on expansion memory. The controller arranges memory assignments of the basic memory in accordance with a first memory map to perform operations of the copying and facsimile functions when the expansion memory is not mounted to the socket. The controller rearranges the memory assignments of the basic memory and of the expansion memory with an effect of expanding the first and second image memory areas in accordance with a second memory map to perform the operations of the copying and facsimile functions when the expansion memory is mounted to the socket.
摘要翻译：多功能设备包括基本存储器，插座和控制器。基本存储器至少包括用于复印功能的第一图像存储区域和用于传真功能的第二图像存储区域。插座连接附加扩展内存。当扩展存储器未安装到插座时，控制器根据第一存储器映射来布置基本存储器的存储器分配，以执行复印和传真功能的操作。控制器重新布置基本存储器和扩展存储器的存储器分配，具有根据第二存储器映射扩展第一和第二映像存储器区域的作用，以在安装扩展存储器时执行复印和传真功能的操作到插座。

65. 发明申请

US20020083288A1 Addressing system for use in storage devices 失效
标题翻译：用于存储设备的寻址系统
公开(公告)号：US20020083288A1
公开(公告)日：2002-06-27
申请号：US10002315
申请日：2001-10-25
申请人： INODE TECHNOLOGY, INC.
发明人： Seong Yong Kim
IPC分类号： G06F012/00
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0658 , G06F3/0683 , G06F12/0623
摘要： Disclosed is a system, which divides a memory into a plurality of equally-sized sub-memories and controls an address of each sub-memory, thereby significantly increasing the access speed to an auxiliary memory unit, which comprises a SCSI (Small Computer System Interface) interface controller for converting a SCSI interface bus into a PCI(Peripheral Component Interconnect Bus) interface bus for use in the system, a memory card module for storing data on the PCI interface bus therein, the memory card module being divided into a plurality of equally-sized memory blocks, and a CPU (Central Processing Unit) module for processing writing data on the PCI interface bus in the memory card module and reading out the data therefrom. The memory card module includes a PCI to memory controller of a tree hierarchical configuration, which is disposed between the PCI interface bus and the plurality of sub-memories as a bridge, for controlling access to the plurality of sub-memories, which is distributed in a hierarchical fashion.
摘要翻译：公开了一种将存储器分成多个相同大小的子存储器并控制每个子存储器的地址的系统，从而显着增加了对辅助存储器单元的访问速度，该辅助存储器单元包括SCSI（小型计算机系统接口）接口控制器，用于将SCSI接口总线转换成用于系统的PCI（外围组件互连总线）接口总线，用于在其中的PCI接口总线上存储数据的存储卡模块，存储卡模块被分成多个用于处理在存储卡模块中的PCI接口总线上写入数据并从其读出数据的CPU（中央处理单元）模块。存储卡模块包括布置在PCI接口总线和多个子存储器之间的作为桥的用于控制对多个子存储器的访问的树分层配置的PCI至存储器控制器，其分布在分层的时尚。

66. 发明授权

US06253302B1 Method and apparatus for supporting multiple overlapping address spaces on a shared bus 失效
公开(公告)号：US06253302B1
公开(公告)日：2001-06-26
申请号：US08705684
申请日：1996-08-29
申请人： Peter D. MacWilliams , Stephen S. Pawlowski
发明人： Peter D. MacWilliams , Stephen S. Pawlowski
IPC分类号： G06F1200
CPC分类号： G06F11/1016 , G06F12/0623
摘要： A method and apparatus for supporting multiple overlapping address spaces on a shared bus includes both an address comparator and an address size indicator. The address comparator compares an address, corresponding to a request to be issued on the bus, to a plurality of address spaces. The address size indicator indicates a first address space of the plurality of address spaces to which the address corresponds.

67. 发明授权

US06198691B1 Force page paging scheme for microcontrollers of various sizes using data random access memory 有权
公开(公告)号：US06198691B1
公开(公告)日：2001-03-06
申请号：US09513427
申请日：2000-02-25
申请人： Randy L. Yach
发明人： Randy L. Yach
IPC分类号： G11C800
CPC分类号： G06F12/0623 , G06F9/30098 , G06F9/30185 , G06F9/34 , H02J13/0027
摘要： A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on a page of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables that are located on a pre-defined page of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in a page select register currently being used by the microcontroller.

68. 发明授权

US6078984A Method of operating a control system which includes a nonvolatile memory unit having memory banks and a volatile memory unit 失效
标题翻译：一种操作控制系统的方法，该控制系统包括具有存储体的非易失性存储单元和易失性存储单元
公开(公告)号：US6078984A
公开(公告)日：2000-06-20
申请号：US824789
申请日：1997-03-26
申请人： Helmut Bubeck
发明人： Helmut Bubeck
IPC分类号： B60R16/02 , B60R16/03 , G06F12/06 , G06F12/02
CPC分类号： B60R16/0315 , G06F12/0623 , G06F12/0638
摘要： The invention is directed to a method of operating a control system which includes a nonvolatile memory unit having memory banks and a volatile memory unit for storing programs and data. Access is permitted to only a single one of the memory banks of the nonvolatile memory unit at a given time point and the memory bank permitting the access is addressable by using addresses which are located within a memory bank address space. The memory bank address space is common to all memory banks and adapted to the size of the memory banks. The nonvolatile memory and the volatile memory are driven in such a manner that the memory bank permitting the access is only accessible in part. When an addressing attempt is made via an address, which is assigned to that part of the particular memory bank which is not accessible, the volatile memory unit is shifted into a state permitting an access and the volatile memory is addressed via the address.
摘要翻译：本发明涉及一种操作控制系统的方法，该控制系统包括具有存储体的非易失性存储器单元和用于存储程序和数据的易失性存储器单元。只允许在给定时间点访问非易失性存储器单元的单个存储器组，并且允许访问的存储体可通过使用位于存储器库地址空间内的地址来寻址。存储体地址空间对于所有存储体来说都是共同的，并且适应于存储体的大小。非易失性存储器和易失性存储器以允许访问的存储体仅部分可访问的方式被驱动。当通过分配给不可访问的特定存储体的该部分的地址进行寻址尝试时，易失性存储器单元被转移到允许访问的状态，并且通过地址寻址易失性存储器。

69. 发明授权

US6055211A Force page zero paging scheme for microcontrollers using data random access memory 失效
标题翻译：使用数据随机存取存储器为单片机强制页面零寻呼方案
公开(公告)号：US6055211A
公开(公告)日：2000-04-25
申请号：US887876
申请日：1997-07-03
申请人： Randy L. Yach
发明人： Randy L. Yach
IPC分类号： G06F9/32 , G06F9/30 , G06F9/318 , G06F9/34 , G06F12/02 , G06F12/06 , H02J13/00 , G11C8/00
CPC分类号： H02J13/0027 , G06F12/0623 , G06F9/30098 , G06F9/30138 , G06F9/30185 , G06F9/34
摘要： A microcontroller architecture that adds a dedicated bit in the op-code decode field to force data access to take place on page 0 of the random access memory (RAM) for that instruction. This allows the user to have any page selected and still have direct access to the special function registers or the register variables which are located on page 0 of the RAM. The setting of the dedicated bit will not affect the current operation of the microcontroller nor will the setting of the bit modify the currently selected address stored in the op-code instruction currently being executed by the microcontroller.
摘要翻译：微控制器架构在操作码解码字段中添加专用位，以强制数据访问在该指令的随机存取存储器（RAM）的第0页上进行。这允许用户选择任何页面，并且仍然可以直接访问位于RAM的第0页上的特殊功能寄存器或寄存器变量。专用位的设置不会影响微控制器的当前操作，也不会对位的设置修改当前由微控制器执行的操作码指令中存储的当前选择的地址。

70. 发明授权

US5991195A Flash EEPROM with erase verification and address scrambling architecture 失效
公开(公告)号：US5991195A
公开(公告)日：1999-11-23
申请号：US803397
申请日：1997-02-20
申请人： Hiromi Nobukata
发明人： Hiromi Nobukata
IPC分类号： G06F12/02 , G06F12/06 , G11C16/16 , G11C16/34 , G11C29/50 , G11C16/06
CPC分类号： G11C16/3409 , G06F12/02 , G06F12/0623 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/50 , G11C29/50004 , G06F2201/81 , G06F2212/2022 , G11C16/04
摘要： In a flash EEPROM where erasing and verifying operations are repeated until the threshold voltages of memory cells reach a predetermined value, a negative voltage is applied, at the time of verification, to the control gate electrode of each cell on a nonselected row, so that the verification is rendered possible despite the existence of any overerased memory cell in the nonselected area, and then the overerased cell is rewritten to be released from the overerased state, whereby the threshold voltage distribution of the memory cells is settable in a narrow range. And by the provision of a means for converting an external designated address to an internal chip address, the storage area designated by the external address is shifted or circulated in the chip every time the data is erased, so that the number of repeatable reprogramming actions is increased apparently in the flash EEPROM.

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