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1. 发明授权

US08213603B2 Encryption processing apparatus 失效
标题翻译：加密处理装置
公开(公告)号：US08213603B2
公开(公告)日：2012-07-03
申请号：US12718052
申请日：2010-03-05
申请人： Hiromi Nobukata
发明人： Hiromi Nobukata
IPC分类号： H04K1/00 , G06F1/16
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/12
摘要： Disclosed herein is an encryption processing apparatus including: a first register device; a second register device; a first flag operation device; a first operation device; a second operation device; a round operation device; a third and a fourth operation device; a second flag operation device; and a fifth operation device.
摘要翻译：这里公开了一种加密处理装置，包括：第一登记装置; 第二寄存器; 第一标志操作装置; 第一操作装置; 第二操作装置; 圆形操作装置; 第三和第四操作装置; 第二标志操作装置; 和第五操作装置。

2. 发明授权

US06581843B2 Record medium and data transferring method using nonvolatile memory 失效
标题翻译：使用非易失性存储器的记录介质和数据传输方法
公开(公告)号：US06581843B2
公开(公告)日：2003-06-24
申请号：US09808958
申请日：2001-03-16
申请人： Hiromi Nobukata
发明人： Hiromi Nobukata
IPC分类号： G06K1906
CPC分类号： G11C7/16 , G11C16/26
摘要： A data transferring method for a nonvolatile memory composed of a flash memory. The flash memory allows a gaplessly read process to be performed unless a transfer error takes place. The flash memory comprises a first shift register, a second shift register, and a switching circuit. The first shift register stores data of the first half area of one page for a data re-transfer process in the case that a transfer error takes place. The second shift register stores data of the second half area of one page for a data re-transfer process in the case that a transfer error takes place. The switching circuit switches between output data of a memory cell array and output data of the first and second shift registers. As a result, data can be transferred at the logically maximum speed. In addition, a transfer error is detected page by page. When a transfer error is detected, the data re-transfer process is performed using the shift registers. Thus, the throughput can be suppressed from deteriorating.
摘要翻译：一种由闪存组成的非易失性存储器的数据传送方法。闪存允许执行无间隙读取的过程，除非发生传输错误。闪速存储器包括第一移位寄存器，第二移位寄存器和开关电路。在发生传送错误的情况下，第一移位寄存器存储用于数据重新传送处理的一页的前半区的数据。在发生传送错误的情况下，第二移位寄存器存储用于数据重新传送处理的一页的第二半区的数据。开关电路在存储单元阵列的输出数据和第一和第二移位寄存器的输出数据之间切换。因此，可以以逻辑最大速度传输数据。另外，逐页检测到传输错误。当检测到传输错误时，使用移位寄存器执行数据重传处理。因此，可以抑制吞吐量恶化。

3. 发明授权

US6058042A Semiconductor nonvolatile memory device and method of data programming the same 有权
标题翻译：半导体非易失性存储器件和数据编程方法相同
公开(公告)号：US6058042A
公开(公告)日：2000-05-02
申请号：US219836
申请日：1998-12-23
申请人： Hiromi Nobukata
发明人： Hiromi Nobukata
IPC分类号： G11C11/56 , G11C16/10 , G11C16/24 , G11C16/34 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C7/1048 , G11C7/18
摘要： A nonvolatile semiconductor memory device having a memory cell in which an amount of charge stored in a charge storage unit changes according to a voltage supplied to a word line and a bit line, a threshold voltage changes according to that change, and data of a value according to the threshold voltage is stored, and writing trinary or more multi-bit data into memory cells in units of pages, provided with a precharging means for precharging all bit lines to a predetermined voltage before the write operation and a write control circuit having a latch circuit by which the write data is latched, making the bit line selected in accordance with an address discharge in accordance with the latch data, and performing write operations in parallel.
摘要翻译：一种具有存储单元的非易失性半导体存储器件，其中存储在电荷存储单元中的电荷量根据提供给字线和位线的电压而改变，阈值电压根据该变化而变化，并且值的数据根据阈值电压被存储，并且以页为单位将三进制或更多个多位数据写入存储单元，该预充电装置具有用于在写操作之前将所有位线预充电到预定电压的预充电装置，以及具有锁存电路，通过该电路使写入数据被锁存，使得根据锁存数据根据地址放电选择位线，并且并行执行写入操作。

4. 发明授权

US07142451B2 Nonvolatile semiconductor memory apparatus and method of producing the same 失效
公开(公告)号：US07142451B2
公开(公告)日：2006-11-28
申请号：US11096017
申请日：2005-04-01
申请人： Ichiro Fujiwara , Hiromi Nobukata
发明人： Ichiro Fujiwara , Hiromi Nobukata
IPC分类号： G11C16/06
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/42332 , H01L29/792
摘要： A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg−Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg−Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

5. 发明授权

US07088622B2 Nonvolatile semiconductor memory apparatus and method of producing the same 失效
公开(公告)号：US07088622B2
公开(公告)日：2006-08-08
申请号：US11095798
申请日：2005-04-01
申请人： Ichiro Fujiwara , Hiromi Nobukata
发明人： Ichiro Fujiwara , Hiromi Nobukata
IPC分类号： G11C16/00
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/42332 , H01L29/792
摘要： A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.

6. 发明授权

US5909395A Flash EEPROM with erase verification and address scrambling architecture 失效
标题翻译：具有擦除验证和地址加扰架构的闪存EEPROM
公开(公告)号：US5909395A
公开(公告)日：1999-06-01
申请号：US708557
申请日：1996-09-06
申请人： Hiromi Nobukata
发明人： Hiromi Nobukata
IPC分类号： G06F12/02 , G06F12/06 , G11C16/16 , G11C16/34 , G11C29/50 , G11C16/04
CPC分类号： G11C16/3409 , G06F12/02 , G06F12/0623 , G11C16/16 , G11C16/344 , G11C16/3445 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/50 , G11C29/50004 , G06F2201/81 , G06F2212/2022 , G11C16/04
摘要： In a flash EEPROM where erasing and verifying operations are repeated until the threshold voltages of memory cells reach a predetermined value, a negative voltage is applied, at the time of verification, to the control gate electrode of each cell on a nonselected row, so that the verification is rendered possible despite the existence of any overerased memory cell in the nonselected area, and then the overerased cell is rewritten to be released from the overerased state, whereby the threshold voltage distribution of the memory cells is settable in a narrow range. And by the provision of a means for converting an external designated address to an internal chip address, the storage area designated by the external address is shifted or circulated in the chip every time the data is erased, so that the number of repeatable reprogramming actions is increased apparently in the flash EEPROM.
摘要翻译：在擦除和验证操作直到存储器单元的阈值电压达到预定值的闪速EEPROM中，在验证时将负电压施加到非选定行上的每个单元的控制栅电极，使得尽管在非选择区域中存在任何过度存储的存储器单元，然后重写过度过的单元以从过渡状态释放，从而使得存储单元的阈值电压分布可在较窄的范围内进行设置。并且通过提供用于将外部指定地址转换为内部芯片地址的装置，每当数据被擦除时，由外部地址指定的存储区域在芯片中被移位或循环，使得可重复的重新编程动作的数量为闪存EEPROM显着增加。

7. 发明申请

US20070217274A1 Nonvolatile memory system and method for controlling nonvolatile memory 失效
标题翻译：用于控制非易失性存储器的非易失性存储器系统和方法
公开(公告)号：US20070217274A1
公开(公告)日：2007-09-20
申请号：US11712627
申请日：2007-03-01
申请人： Hiromi Nobukata
发明人： Hiromi Nobukata
IPC分类号： G11C29/00
CPC分类号： G11C16/22 , G11C5/143 , G11C16/30
摘要： A nonvolatile memory system includes a drive voltage generator to generate a drive voltage on the basis of a power supply voltage; a plurality of normal memory cells serving as a nonvolatile memory storing data by accumulating charge of a polarity according to the data to be stored in a floating gate at a level according to the drive voltage generated by the drive voltage generator, the data being written in or read from the nonvolatile memory; a minimum voltage detecting memory cell serving as a nonvolatile memory in which charge of a level to cause a read error when the power supply voltage is equal to or lower than a minimum voltage of predetermined operation guarantee is accumulated in a floating gate; and a controller to output a read result of the normal memory cells if no read error occurs in a reading operation in the minimum voltage detecting memory cell.
摘要翻译：非易失性存储器系统包括：驱动电压发生器，用于基于电源电压产生驱动电压; 用作非易失性存储器的多个正常存储单元，其通过根据由驱动电压发生器产生的驱动电压的电平累积根据要存储在浮动栅极中的数据的极性的电荷来存储数据，数据被写入或从非易失性存储器读取; 用作非易失性存储器的最小电压检测存储单元，其中当电源电压等于或低于预定操作保证的最小电压时导致读错误的电平的电荷被积累在浮动栅极中; 以及控制器，如果在最小电压检测存储单元中的读取操作中没有发生读取错误，则输出正常存储器单元的读取结果。

8. 发明授权

US06903977B2 Nonvolatile semiconductor memory device and method of producing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06903977B2
公开(公告)日：2005-06-07
申请号：US10432158
申请日：2002-09-25
申请人： Ichiro Fujiwara , Hiromi Nobukata
发明人： Ichiro Fujiwara , Hiromi Nobukata
IPC分类号： G11C16/04 , H01L21/8246 , H01L27/105 , H01L29/423 , H01L29/792 , G11C16/00
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L29/42332 , H01L29/792
摘要： A nonvolatile semiconductor memory apparatus suitable to logic incorporation, by which a charge injection efficiency is high and hot electrons (HE) can be effectively injected at a low voltage is provided. A memory transistor (M) comprises first and second source/drain regions (S, SSL, D, SBL) formed on a semiconductor substrate (SUB, W), a charge storage film (GD) having a charge storage faculty and a gate electrode (WL). Memory peripheral circuits (2a to 9) generate a first voltage (Vd) and a second voltage (Vg-Vwell), apply the first voltage (Vd) to the second source/drain region (D, SBL) by using potential (0V) of the first source/drain region (S, SSL) as reference, apply the second voltage (Vg-Vwell) to the gate electrode (WL), generate hot electrons (HE) by ionization collision on the second source/drain region (D, SBL) side, and inject the hot electrons (HE) to the charge storage film (GD) from the second source/drain region (D, SBL) side at the time of writing data.
摘要翻译：提供了适用于电荷注入效率高的逻辑结合的非易失性半导体存储器件，并且可以以低电压有效地注入热电子（HE）。存储晶体管（M）包括形成在半导体衬底（SUB，W）上的第一和第二源/漏区（S，SSL，D，SBL），具有电荷存储层的电荷存储膜（GD）（WL）。存储器外围电路（2 a至9）产生第一电压（Vd）和第二电压（Vg-Vwell），通过使用电位（0V）将第一电压（Vd）施加到第二源/漏区（D，SBL））作为参考，将第二电压（Vg-Vwell）施加到栅电极（WL），通过在第二源极/漏极区域上的电离碰撞产生热电子（HE） D，SBL）侧，并且在写入数据时从第二源/漏区（D，SBL）侧将热电子（HE）注入到电荷存储膜（GD）。

9. 发明授权

US6046933A Nonvolatile semiconductor memory device and IC memory card using same 失效
标题翻译：非易失性半导体存储器件和使用其的IC存储卡
公开(公告)号：US6046933A
公开(公告)日：2000-04-04
申请号：US203597
申请日：1998-12-02
申请人： Hiromi Nobukata , Yoshitaka Osaka , Ihachi Naiki
发明人： Hiromi Nobukata , Yoshitaka Osaka , Ihachi Naiki
IPC分类号： G11C16/06 , G06K19/07 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/08 , G11C11/34
CPC分类号： G11C11/5621 , G11C16/0483 , G11C16/08 , G11C2211/5641
摘要： A nonvolatile semiconductor memory device capable of improving a reliability of a spare region, capable of improving the reliability of a data region in accordance with a method of use, and capable of realizing a function of an additional writing as a multi-level memory, and an IC memory card using the same, provided with a data region capable of storing 4-level and binary data; a spare region capable of storing binary data; data region use decoders for supplying a drive voltage to the data region; spare region use decoders and for supplying the drive voltage to the spare region; a latch circuit for transferring data with the data region in accordance with the number of levels of the multi-level data to be stored in the data region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally completed; and a latch circuit for transferring data with the spare region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally completed.
摘要翻译：一种能够提高备用区域的可靠性的非易失性半导体存储器件，其能够根据使用方法提高数据区域的可靠性，并且能够实现附加写入作为多级存储器的功能;以及使用该IC存储卡的IC存储卡，具有能够存储4级和二进制数据的数据区域; 能够存储二进制数据的备用区域; 数据区域使用解码器，用于向数据区域提供驱动电压; 备用区域使用解码器并将驱动电压提供给备用区域; 一个锁存电路，用于根据要存储在数据区域中的多电平数据的电平数量与数据区传输数据，并且当数据传输正常完成时停止提供副解码器的驱动电压 ; 以及用于在备用区域传送数据并在数据传送正常完成时停止提供副解码器的驱动电压的锁存电路。

10. 发明授权

US5822248A Non-volatile semiconductor memory device using folded bit line architecture 失效
标题翻译：使用折叠位线架构的非易失性半导体存储器件
公开(公告)号：US5822248A
公开(公告)日：1998-10-13
申请号：US559151
申请日：1995-11-17
申请人： Kenichi Satori , Hiromi Nobukata
发明人： Kenichi Satori , Hiromi Nobukata
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , G11C16/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0416 , G11C16/28
摘要： A non-volatile memory device which enables use of a folded bit line system includes odd and even main bit lines, a plurality of sub-bit lines connected to the main bit lines through selection gates. Conductive and non-conductive states of the selection gate connecting to the odd main bit line and the selection gate connecting to the even main bit line are controlled by different selection signal lines so that the odd main bit line and the even bit line are operated selectively.
摘要翻译：能够使用折叠位线系统的非易失性存储器件包括奇数和偶数主位线，通过选择栅极连接到主位线的多个子位线。连接到奇数主位线的选择栅极和连接到偶数主位线的选择栅极的导电和非导通状态由不同的选择信号线控制，使得奇数主位线和偶位线选择性地被操作。

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