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61. 发明授权

US06396344B1 Amplifier linearization by learned linear behavior 失效
标题翻译：通过学习的线性行为放大器线性化
公开(公告)号：US06396344B1
公开(公告)日：2002-05-28
申请号：US08785752
申请日：1997-01-18
申请人： Charles Gentzler , Zvi Regev
发明人： Charles Gentzler , Zvi Regev
IPC分类号： H03F126
CPC分类号： H03F1/3294 , H03F1/3247 , H03F2200/102
摘要： This invention relates to the Linearization of multitone or multiple signal amplifiers or like devices. The telecommunications industry is currently employing amplifiers, transmitters or other active devices that are not only amplifying complex digital and analog modulation formats, but are transmitting or amplifying multiple complex signals simultaneously. In order to meet the transmission requirements, amplifiers or transmitters must exhibit extreme phase and amplitude linearity. Deviations from linearity are distortions which lead to intermodulation of the signal components; those intermodulation products appear variously through out the spectrum and cause interference between signals, which in turn degrades the amplified signals. Today the amplification of these signals requires the use of feedforward technology to achieve the performance required to meet government spectrum modulation mask requirements. This invention provides an important advance in the art of extreme phase and amplitude linearity.
摘要翻译：本发明涉及多声道或多信号放大器或类似装置的线性化。电信业目前正在使用放大器，发射机或其他有源器件，它们不仅可以放大复杂的数字和模拟调制格式，而且可以同时传输或放大多个复杂信号。为了满足传输要求，放大器或发射机必须具有极端的相位和幅度线性度。与线性的偏差是导致信号分量互调的失真; 这些互调产物出现在频谱之外，并引起信号之间的干扰，这又会降低放大的信号。今天，这些信号的放大需要使用前馈技术来实现满足政府频谱调制掩模要求所需的性能。本发明提供了极端相位和振幅线性领域的重要进步。

62. 发明授权

US08438345B2 Multi-priority encoder 有权
标题翻译：多优先编码器
公开(公告)号：US08438345B2
公开(公告)日：2013-05-07
申请号：US13175479
申请日：2011-07-01
申请人： Zvi Regev
发明人： Zvi Regev
IPC分类号： G06F7/74
CPC分类号： G11C15/04 , G06F7/74 , G06F17/30982 , G11C15/00 , H03M1/00 , H04L45/7453
摘要： A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.
摘要翻译：多优先级编码器包括以优先级顺序排列的多个互连的单优先级编码器。多优先级编码器包括用于如果较高级别的单优先级编码器输出匹配输出则阻止由较低级单优先级编码器匹配输出的电路。从内容可寻址存储器接收匹配数据，并且优先级编码器包括用于输出由最高优先级指示符标记的每个最高优先级匹配线的地址位置的地址编码电路。每个单优先级编码器包括具有多个指示符段的最高优先级指示符，每个指示符段与匹配行输入相关联。

63. 发明申请

US20110075681A1 HIGH SPEED RING/BUS 有权
标题翻译：高速环/总线
公开(公告)号：US20110075681A1
公开(公告)日：2011-03-31
申请号：US12961262
申请日：2010-12-06
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： H04L12/42
CPC分类号： H04L12/422 , H04L12/42
摘要： A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node includes an output port coupled to a media segment that it exclusively controls. And an input port coupled to a media segment that is exclusively controlled by another node of the bus. Each media segment typically includes a plurality of high speed data channels such as electrical transmission lines.
摘要翻译：一种数据通信总线及其操作方法，包括连接到相应的多个媒体段的多个节点。典型的节点包括耦合到其专门控制的媒体段的输出端口。以及耦合到由总线的另一个节点专门控制的媒体段的输入端口。每个媒体段通常包括多个高速数据信道，例如电传输线路。

64. 发明授权

US07831765B2 Distributed programmable priority encoder capable of finding the longest match in a single operation 有权
标题翻译：分布式可编程优先编码器能够在单次操作中找到最长的匹配
公开(公告)号：US07831765B2
公开(公告)日：2010-11-09
申请号：US11484854
申请日：2006-07-12
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.
摘要翻译：一种用于内容可寻址存储器（CAM）设备的分布式，分层结构化的可编程优先级编码器，其包括至少一个部分，所述部分还包括部分级别优先级编码器和多个块，每个块还包括块级优先级编码器，以及多个切片。分布式，分层结构化的可编程优先级编码器，其中每个切片还包括CAM切片，耦合到CAM切片的可屏蔽比较寄存器和耦合到所述CAM切片的可编程优先编码器，并进一步耦合到所述块级优先级编码器。

65. 发明授权

US07386660B2 CAM with automatic writing to the next free address 有权
标题翻译： CAM自动写入下一个空闲地址
公开(公告)号：US07386660B2
公开(公告)日：2008-06-10
申请号：US11581747
申请日：2006-10-17
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00
CPC分类号： G11C15/00
摘要： A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the event of a non-match, the new data can be written to the invalid locations in a single clock cycle.
摘要翻译：公开了一种用于将非匹配数据自动写入内容寻址存储器（CAM）内的非有效位置的方法和装置。与匹配地址的搜索过程同时确定非有效位置，使得在不匹配的情况下，可以在单个时钟周期内将新数据写入无效位置。

66. 发明授权

US07362637B2 Current switching sensor detector 有权
标题翻译：电流开关传感器检测器
公开(公告)号：US07362637B2
公开(公告)日：2008-04-22
申请号：US10978464
申请日：2004-11-02
申请人： Zvi Regev , Alon Regev
发明人： Zvi Regev , Alon Regev
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/062 , G11C15/04 , G11C2207/063
摘要： A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the switching circuit. The sensor also includes a current limit control circuit coupled to each of the current limiters. The sensor is effectively shielded from the effect of parasitic capacitance in the switching device because the current flow through the switching circuit reacts immediately and without regard to the level of parasitic capacitance whenever the switching circuit makes a state change.
摘要翻译：用于开关电路的传感器通过监视通过开关电路的电流来检测开关电路的逻辑状态。电流通过与开关电路串联耦合的一个或多个限流器和电压调节器来调节。传感器还包括耦合到每个限流器的限流控制电路。传感器被有效地屏蔽开关器件中的寄生电容的影响，因为只要切换电路进行状态改变，电流流经开关电路就会立即反应，而不考虑寄生电容的电平。

67. 发明授权

US07330929B2 CAM modified to be used for statistic calculation in network switches and routers 有权
标题翻译： CAM修改用于网络交换机和路由器的统计计算
公开(公告)号：US07330929B2
公开(公告)日：2008-02-12
申请号：US11436994
申请日：2006-05-19
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/90
摘要： A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if there are multiple matching entries, in some instances only one matching entry has its counter incremented. The counter value can be written or read as part of either the least significant or most significant bits of the CAM entry.
摘要翻译：内容可寻址存储器（CAM）设备包括多个条目，每个条目具有关联的计数器。当CAM条目匹配存储在CAM设备的比较寄存器中的搜索字时，匹配条目的计数器可以递增。或者，如果存在多个匹配条目，则在某些情况下，只有一个匹配条目的计数器递增。计数器值可以被写入或读取作为CAM入口的最低有效位或最高有效位的一部分。

68. 发明申请

US20070168779A1 Testing of a CAM 审中-公开
标题翻译： CAM测试
公开(公告)号：US20070168779A1
公开(公告)日：2007-07-19
申请号：US11474496
申请日：2006-06-26
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G11C29/10 , G11C29/36
摘要： A system and method for validating a memory device using a Gray Code is described. The system and method tests data segments of a memory storage location concurrently, where a data segment may be a nibble. Each data segment cycles through the possible Gray Code states. Once a data segment, and therefore each data segment because of the concurrency, cycles through the possible Gray code states, the memory device is completely tested. A memory device may, in particular, be a content addressable memory (CAM). A method for testing a priority encoder of a CAM using a Gray Code is also described. Each memory storage location is loaded with a predetermined Gray code representing the address of the memory storage location, each memory storage location differs from an adjacent memory storage location by one data bit.
摘要翻译：描述使用格雷码验证存储器件的系统和方法。系统和方法同时测试存储器存储位置的数据段，其中数据段可以是半字节。每个数据段循环可能的格雷码状态。一旦数据段，因此由于并发性而导致每个数据段循环通过可能的格雷码状态，则存储器件被完全测试。特别地，存储器件可以是内容可寻址存储器（CAM）。还描述了使用格雷码测试CAM的优先编码器的方法。每个存储器存储位置被加载有表示存储器存储位置的地址的预定格雷码，每个存储器存储位置与相邻存储器存储位置不同一个数据位。

69. 发明申请

US20070085571A1 Signal presence detector 失效
标题翻译：信号存在检测器
公开(公告)号：US20070085571A1
公开(公告)日：2007-04-19
申请号：US11493149
申请日：2006-07-25
申请人： Zvi Regev
发明人： Zvi Regev
IPC分类号： H03K5/19
CPC分类号： H03F3/217 , H03F2200/78 , H03K5/125 , H03K5/19 , H04L25/45
摘要： A signal presence detection device has a first reference voltage generation device in the form of a first voltage divider, a second reference voltage generation device in the form of a second voltage divider and a third reference voltage generation device in the form of a third voltage divider. The detection device also has a signal conditioning device such as a hysteretic amplifier with an output that is coupled to the first and second voltage dividers. A comparison device is coupled to all three voltage dividers to compare a voltage of the first voltage divider to a voltage of the third voltage divider and to compare a voltage of the second voltage divider to the voltage of the third voltage divider. The comparison device is coupled at two outputs thereof to two respective inputs of an XOR device. The XOR device receives respective signals from the first and second outputs of the comparison device and produces a signal presence output that serves to indicate whether an incoming signal is present or absent.
摘要翻译：信号存在检测装置具有第一分压器形式的第一参考电压产生装置，第二分压器形式的第二参考电压产生装置和第三分压器形式的第三参考电压产生装置。检测装置还具有信号调节装置，例如具有耦合到第一和第二分压器的输出的滞后放大器。比较装置耦合到所有三个分压器，以将第一分压器的电压与第三分压器的电压进行比较，并将第二分压器的电压与第三分压器的电压进行比较。比较装置在其两个输出处耦合到XOR装置的两个相应的输入端。 XOR设备从比较设备的第一和第二输出接收相应的信号，并产生用于指示输入信号是存在还是不存在的信号存在输出。

70. 发明申请

US20070005878A1 CAM modified to be used for statistic calculation in network switches and routers 有权
标题翻译： CAM修改用于网络交换机和路由器的统计计算
公开(公告)号：US20070005878A1
公开(公告)日：2007-01-04
申请号：US11436994
申请日：2006-05-19
申请人： Alon Regev , Zvi Regev
发明人： Alon Regev , Zvi Regev
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/90
摘要： A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if there are multiple matching entries, in some instances only one matching entry has its counter incremented. The counter value can be written or read as part of either the least significant or most significant bits of the CAM entry.
摘要翻译：内容可寻址存储器（CAM）设备包括多个条目，每个条目具有关联的计数器。当CAM条目匹配存储在CAM设备的比较寄存器中的搜索字时，匹配条目的计数器可以递增。或者，如果存在多个匹配条目，则在某些情况下，只有一个匹配条目的计数器递增。计数器值可以写入或读取作为CAM入口的最低有效位或最高有效位的一部分。

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