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61. 发明授权

US08120887B2 MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage 有权
标题翻译： MOS晶体管触发瞬态电压抑制器以在较低电压下提供电路保护
公开(公告)号：US08120887B2
公开(公告)日：2012-02-21
申请号：US11712317
申请日：2007-02-28
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H02H3/22 , H02H9/00
CPC分类号： H01L27/0262 , Y10T29/49002
摘要： An electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled to a second BJT to form a SCR functioning as a main clamp circuit of the TVS circuit. The TVS circuit further includes a triggering circuit for generating a triggering signal for the triggering MOS transistor wherein the triggering circuit includes multiple stacked MOS transistors for turning into a conductive state by a transient voltage while maintaining a low leakage current.
摘要翻译：一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在与第二BJT耦合的第一双极结晶体管（BJT）的发射极和集电极之间的触发MOS晶体管，以形成用作TVS电路的主钳位电路的SCR。 TVS电路还包括用于产生用于触发MOS晶体管的触发信号的触发电路，其中触发电路包括多个堆叠的MOS晶体管，用于在保持低泄漏电流的同时通过瞬态电压转为导通状态。

62. 发明申请

US20110300678A1 Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch 有权
标题翻译：对称阻塞瞬态电压抑制器（TVS）采用双极晶体管基极抢夺
公开(公告)号：US20110300678A1
公开(公告)日：2011-12-08
申请号：US13136738
申请日：2011-08-08
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L21/8238
CPC分类号： H01L27/0259 , Y10T29/49002
摘要： A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
摘要翻译：用于抑制瞬态电压的对称阻塞瞬态电压抑制（TVS）电路包括具有电连接到两个晶体管的公共源的基极的NPN晶体管，由此基极连接到正或负的低电位的端子电压瞬变。两个晶体管是用于实现基本上对称的双向钳位瞬态电压的两个基本相同的晶体管。这两个晶体管还包括具有电互连源的第一和第二MOSFET晶体管。第一MOSFET晶体管还包括连接到高电位端子的漏极和连接到低电位端子的栅极，并且第二MOSFET晶体管还包括连接到低电位端子的端子的漏极和连接到高电位的栅极潜在终端。

63. 发明申请

US20090261883A1 Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch 有权
标题翻译：对称阻塞瞬态电压抑制器（TVS）采用双极晶体管基极抢夺
公开(公告)号：US20090261883A1
公开(公告)日：2009-10-22
申请号：US12456948
申请日：2009-06-25
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H03K5/08 , H01S4/00
CPC分类号： H01L27/0259 , Y10T29/49002
摘要： A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
摘要翻译：用于抑制瞬态电压的对称阻塞瞬态电压抑制（TVS）电路包括具有电连接到两个晶体管的公共源的基极的NPN晶体管，由此基极连接到正或负的低电位的端子电压瞬变。两个晶体管是用于实现基本上对称的双向钳位瞬态电压的两个基本相同的晶体管。这两个晶体管还包括具有电互连源的第一和第二MOSFET晶体管。第一MOSFET晶体管还包括连接到高电位端子的漏极和连接到低电位端子的栅极，并且第二MOSFET晶体管还包括连接到低电位端子的端子的漏极和连接到高电位的栅极潜在终端。

64. 发明申请

US20080310065A1 Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS 有权
标题翻译：在TVS对称和不对称EMI滤波器中实现线性电容的方法
公开(公告)号：US20080310065A1
公开(公告)日：2008-12-18
申请号：US12080104
申请日：2008-04-01
申请人： Moses Ho , Madhur Bobde , Mike Chang , Limin Weng
发明人： Moses Ho , Madhur Bobde , Mike Chang , Limin Weng
IPC分类号： H02H9/04
CPC分类号： H01L27/0676 , H01L23/552 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.
摘要翻译：具有与第一导电类型的半导体衬底上支持的电磁干扰（EMI）滤波器集成的具有单向阻塞和对称双向阻塞能力的瞬态电压抑制（TVS）电路。与EMI滤波器集成的TVS电路还包括设置在用于对称双向阻塞结构的表面上的接地端子和用于单向阻塞结构的半导体衬底的底部以及设置在单向阻断结构上的输入和输出端子具有至少齐纳二极管的顶表面和设置在半导体衬底中的多个电容器，以将接地端子连接到具有直接电容耦合而不具有中间浮体区域的输入和输出端子。

65. 发明申请

US20070073807A1 Latch-up free vertical TVS diode array structure using trench isolation 有权
标题翻译：立式TVS二极管阵列结构采用沟槽隔离
公开(公告)号：US20070073807A1
公开(公告)日：2007-03-29
申请号：US11606602
申请日：2006-11-30
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： G06F15/16 , H01L29/76
CPC分类号： H01L29/66727 , H01L29/0623 , H01L29/1095 , H01L29/407 , H01L29/66734 , H01L29/7811 , H01L29/782
摘要： A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.
摘要翻译：一种用于制造基本上遵循用于制造垂直半导体功率器件的制造工艺的瞬态电压抑制（TVS）阵列的方法。该方法包括在半导体衬底中打开第一导电类型的外延层中的多个隔离沟槽的步骤，然后施加用于在两个隔离沟槽之间掺杂具有第二导电类型的体区的体掩模。该方法还包括施加用于注入构成多个二极管的第一导电类型的多个掺杂区域的源极掩模的步骤，其中隔离沟槽由于掺杂区域之间的闩锁而隔离和防止寄生PNP或NPN晶体管的不同导电类型。

66. 发明授权

US09620584B2 Integrated Schottky diode in high voltage semiconductor device 有权
公开(公告)号：US09620584B2
公开(公告)日：2017-04-11
申请号：US14454696
申请日：2014-08-07
申请人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
发明人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/739
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0834 , H01L29/1095 , H01L29/404 , H01L29/42368 , H01L29/4916 , H01L29/512 , H01L29/66333 , H01L29/66712 , H01L29/7393 , H01L29/7395 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

67. 发明授权

US09478646B2 Methods for fabricating anode shorted field stop insulated gate bipolar transistor 有权
标题翻译：制造阳极短路绝缘栅双极晶体管的方法
公开(公告)号：US09478646B2
公开(公告)日：2016-10-25
申请号：US13192385
申请日：2011-07-27
申请人： Anup Bhalla , Madhur Bobde , Yongping Ding , Xiaotian Zhang , Yueh-Se Ho
发明人： Anup Bhalla , Madhur Bobde , Yongping Ding , Xiaotian Zhang , Yueh-Se Ho
IPC分类号： H01L29/739 , H01L29/66 , H01L29/06 , H01L29/08
CPC分类号： H01L29/7395 , H01L21/2636 , H01L21/26513 , H01L21/266 , H01L21/761 , H01L29/0615 , H01L29/0638 , H01L29/0661 , H01L29/0696 , H01L29/0834 , H01L29/66333
摘要： A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
摘要翻译：用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。外延层可以在衬底上或场停止层上生长。在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

68. 发明授权

US08933506B2 Diode structures with controlled injection efficiency for fast switching 有权
标题翻译：具有控制注入效率的二极管结构，实现快速切换
公开(公告)号：US08933506B2
公开(公告)日：2015-01-13
申请号：US12931429
申请日：2011-01-31
申请人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
发明人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
IPC分类号： H01L29/66 , H01L29/739
CPC分类号： H01L29/7391
摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体器件。半导体器件包括在第一主表面上的第一导电类型的第一半导体层。半导体器件还包括在与第一主表面相对的第二主表面上的第二导电类型的第二半导体层。该半导体器件还包括设置在第二半导体层正下方的第一导电类型的注入效率控制缓冲层，以控制第二半导体层的注入效率。

69. 发明授权

US08859361B1 Symmetric blocking transient voltage suppressor (TVS) using bipolar NPN and PNP transistor base snatch 有权
标题翻译：对称阻塞瞬态电压抑制器（TVS）使用双极性NPN和PNP晶体管基极抢夺
公开(公告)号：US08859361B1
公开(公告)日：2014-10-14
申请号：US13857146
申请日：2013-04-05
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L27/02
CPC分类号： H01L27/0259
摘要： A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
摘要翻译：用于抑制瞬态电压的对称阻塞瞬态电压抑制（TVS）电路包括具有电连接到两个晶体管的公共源的基极的NPN晶体管，由此基极连接到正或负的低电位的端子电压瞬变。两个晶体管是用于实现基本上对称的双向钳位瞬态电压的两个基本相同的晶体管。这两个晶体管还包括具有电互连源的第一和第二MOSFET晶体管。第一MOSFET晶体管还包括连接到高电位端子的漏极和连接到低电位端子的栅极，并且第二MOSFET晶体管还包括连接到低电位端子的端子的漏极和连接到高电位的栅极潜在终端。

70. 发明授权

US08558275B2 Sawtooth electric field drift region structure for power semiconductor devices 有权
公开(公告)号：US08558275B2
公开(公告)日：2013-10-15
申请号：US12006399
申请日：2007-12-31
申请人： Madhur Bobde
发明人： Madhur Bobde
IPC分类号： H01L29/74
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/66128 , H01L29/66712 , H01L29/7395 , H01L29/8611
摘要： This invention discloses a semiconductor power device formed in a semiconductor substrate. The semiconductor power device further includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP

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