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61. 发明授权

US4934820A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4934820A
公开(公告)日：1990-06-19
申请号：US256862
申请日：1988-10-12
申请人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka
发明人： Yasushi Takahashi , Kazuyuki Miyazawa , Hidetoshi Iwai , Masaya Muranaka
IPC分类号： H01L21/60 , G11C11/401 , H01L23/495 , H01L23/50
CPC分类号： H01L24/49 , H01L23/4951 , H01L23/49541 , H01L23/49555 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48624 , H01L2224/49171 , H01L2224/73265 , H01L2224/85424 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/181 , H01L2924/3011
摘要： According to the present invention, a semiconductor chip is mounted on a zigzag in-line type package (ZIP) partially using a tabless lead frame and bonding pads are arranged on the chip so that the chip can be applied also to other different types of packages. As different types of packages there are a small out-line J-bent type package (SOJ) for which there is used a lead frame with tab and a dual in-line type package (DIP) for which there is used a tabless lead frame. Further, a plurality of bonding pad pairs are provided among the bonding pads on the chip each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to readily facilitate, or make compatible, the semiconductor chip to a variety of or different types of packages.
摘要翻译：根据本发明，半导体芯片部分地使用无引线引线框安装在Z字形在线型封装（ZIP）上，并且焊盘布置在芯片上，使得芯片也可以应用于其他不同类型的封装。作为不同类型的封装，有一个小型的外部J型弯曲型封装（SOJ），其中使用了带有引脚的引线框架和双列直插式封装（DIP），其中使用无引脚引线框架。此外，在芯片上的接合焊盘之间设置多个接合焊盘对，这样的焊盘对的每个焊盘具有与其相关的另一焊盘相同的功能，从而在半导体芯片上的不同接合焊盘中复制共同的功能，以便容易地将半导体芯片促进或兼容到各种或不同类型的封装。

62. 发明授权

US4818995A Parallel transmission system 失效
标题翻译：并行传输系统
公开(公告)号：US4818995A
公开(公告)日：1989-04-04
申请号：US51519
申请日：1987-05-19
申请人： Yoshitaka Takahashi , Yasushi Takahashi , Yukio Nakano , Akihiro Hori , Minoru Maeda , Yoshihiko Miyano , Ikuo Tokizawa , Masatoyo Sumida
发明人： Yoshitaka Takahashi , Yasushi Takahashi , Yukio Nakano , Akihiro Hori , Minoru Maeda , Yoshihiko Miyano , Ikuo Tokizawa , Masatoyo Sumida
IPC分类号： H04L7/00 , H04L7/02 , H04L25/02 , H04L25/14 , H04L25/40 , H03M7/00
CPC分类号： H04L7/0066 , H04L25/14
摘要： A parallel pulse transmission system, wherein the sending side converts original signals into line coded signals of a block coding type (mBnB line codes, m/2.gtoreq.2/3, n.gtoreq.3) and transmits them after aligning the timings of the blocks receiving side. The regenerates of the systems transmitted line codes and thereafter, aligns the timings of blocks of the line codes.
摘要翻译：一种并行脉冲传输系统，其中发送侧将原始信号转换为块编码类型（mBnB行码，m / 2> / = 2/3，n> / = 3）的行编码信号，并在对准定时的块接收侧。系统的再生发送线路代码，此后，对齐线路代码块的定时。

63. 发明授权

US4708944A Protease adsorbent and process for purifying TPA utilizing the same 失效
标题翻译：蛋白酶吸附剂和使用其的TPA纯化方法
公开(公告)号：US4708944A
公开(公告)日：1987-11-24
申请号：US749713
申请日：1985-06-28
申请人： Tetsuya Someno , Kazuo Kato , Yasushi Takahashi , Shinichi Ishii , Tomio Takeuchi , Hamao Umezawa
发明人： Tetsuya Someno , Kazuo Kato , Yasushi Takahashi , Shinichi Ishii , Tomio Takeuchi , Hamao Umezawa
IPC分类号： C07K17/02 , B01J20/32 , C07K1/22 , C07K17/00 , C12N9/50 , C12N9/64 , C12N9/72 , B01J37/36
CPC分类号： C12N9/6459 , B01J20/321 , B01J20/3212 , B01J20/3251 , C12N9/50 , C12Y304/21069
摘要： A protease adsorbent wherein valyl-glycyl-argininal is bound to a water-insoluble carrier and a process for purifying TPA utilizing the same.
摘要翻译：其中缬氨酰 - 甘氨酰 - 精氨酸与水不溶性载体结合的蛋白酶吸附剂和利用该蛋白酶吸附剂纯化TPA的方法。

64. 发明授权

US3932374A Bleomycinic acid and process for preparing thereof 失效
标题翻译：博来霉素酸及其制备方法
公开(公告)号：US3932374A
公开(公告)日：1976-01-13
申请号：US479087
申请日：1974-06-13
申请人： Hamao Umezawa , Yasushi Takahashi , Tadashi Shirai , Akio Fujii
发明人： Hamao Umezawa , Yasushi Takahashi , Tadashi Shirai , Akio Fujii
IPC分类号： C07H15/26 , C07C103/52 , A61K37/00
CPC分类号： C07H15/26
摘要： A process for preparing bleomycinic acid having a melting point of 228.degree.-230.degree.C. (decomposition) and an analysis of C : 40.80%, H : 5.29%, N : 16.45%, O : 24.78%, S : 4.53%, Cl : 3.37%, and Cu : 4.78% which is characterized by being soluble in water, difficultly soluble in methanol, acetic acid and dimethylsulfoxide, and insoluble in ethanol, ethyl acetate, acetone and ether, and which tests positive to Pauly and Ehrlich reactions but tests negative to ninhydrin, Sakaguchi, Dragendorf, Tollens, ferric chloride, Fehling and Molish reactions, and which has a maximum ultraviolet absorption spectrum at 246 m.mu. and 292 m.mu. and which has an infrared absorption spectrum bands at 3350, 1720, 1670, 1640, 1580, 1460, 1365, 1050, 770 (cm.sup.-.sup.1), and which can be hydrolyzed to yield 2'-(2-aminoethyl)-2,4'-bithiazole-4-carboxylic acid, L-threonine, 4-amino-3-hydroxy-2-methyl-.eta.-valeric acid, .beta.-hydroxy-histidine, .beta.-amino-.beta.-(4-amino-6-carboxy-5-methylpyrimidine-2-yl)-propionic acid, L-.beta.-amino-alanine, L-gulose and 3-0-carbamoyl-D-mannose, which comprises hydrolyzing bleomycin in the presence of a mycelium mass or enzyme.
摘要翻译：制备熔点为228〜-230℃的博来霉素酸（分解），C：40.80％，H：5.29％，N：16.45％，O：24.78％，S：4.53％的分析方法， Cl：3.37％，Cu：4.78％，其特征在于可溶于水，难溶于甲醇，乙酸和二甲基亚砜，不溶于乙醇，乙酸乙酯，丙酮和乙醚，并对Pauly和Ehrlich反应进行检测但对茚三酮，Sakaguchi，Dragendorf，Tollens，氯化铁，Fehling和Molish反应阴性测试，其最大紫外吸收光谱为246μm和292μm，红外吸收光谱带为3350,1720,1670 ，1640,1580,1460,1365,1050,770（cm -1），并可水解得到2' - （2-氨基乙基）-2,4'-联噻唑-4-羧酸，L- 苏氨酸，4-氨基-3-羟基-2-甲基 - 戊酸，β-羟基 - 组氨酸，β-氨基-β-（4-氨基-6-羧基-5-甲基嘧啶-2-基） - 丙酸一个 cid，L-β-氨基 - 丙氨酸，L-古洛糖和3-0-氨基甲酰-D-甘露糖，其包括在菌丝体或酶存在下水解博来霉素。

65. 发明授权

US08654557B2 Semiconductor memory device, information processing system including the same, and controller 有权
标题翻译：半导体存储器件，包括其的信息处理系统和控制器
公开(公告)号：US08654557B2
公开(公告)日：2014-02-18
申请号：US13593046
申请日：2012-08-23
申请人： Yasushi Takahashi , Toru Ishikawa
发明人： Yasushi Takahashi , Toru Ishikawa
IPC分类号： G11C5/06
CPC分类号： G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： A system including a controller and a memory chip. The controller includes first and second selection signal terminals supplying first and second selection signals, respectively, multiple first data terminals and multiple second data terminals. The memory chip includes a semiconductor substrate, third and fourth selection signal terminals provided on the semiconductor substrate and electrically coupled to the first and second selection signal terminals of the controller, respectively. Multiple third data terminals are provided on the semiconductor substrate and electrically coupled to the first data terminals of the controller, respectively. Multiple fourth data terminals are provided on the semiconductor substrate and electrically coupled to the second data terminals of the controller, respectively. The first and third data terminals communicate first data in response to the first selection signal. The second and fourth data terminals communicate second data in response to the second selection signal.
摘要翻译：一种包括控制器和存储器芯片的系统。控制器包括分别提供第一和第二选择信号的第一和第二选择信号端，多个第一数据终端和多个第二数据终端。存储器芯片包括半导体衬底，设置在半导体衬底上并分别电耦合到控制器的第一和第二选择信号端子的第三和第四选择信号端子。多个第三数据端子分别设置在半导体衬底上并电连接到控制器的第一数据端。多个第四数据端子分别设置在半导体衬底上并电连接到控制器的第二数据端。第一和第三数据终端响应于第一选择信号来传送第一数据。第二和第四数据终端响应于第二选择信号传送第二数据。

66. 发明授权

US08455986B2 Mosfet package 失效
标题翻译： Mosfet包装
公开(公告)号：US08455986B2
公开(公告)日：2013-06-04
申请号：US13459839
申请日：2012-04-30
申请人： Ryoichi Kajiwara , Masahiro Koizumi , Toshiaki Morita , Kazuya Takahashi , Munehisa Kishimoto , Shigeru Ishii , Toshinori Hirashima , Yasushi Takahashi , Toshiyuki Hata , Hiroshi Sato , Keiichi Ookawa
发明人： Ryoichi Kajiwara , Masahiro Koizumi , Toshiaki Morita , Kazuya Takahashi , Munehisa Kishimoto , Shigeru Ishii , Toshinori Hirashima , Yasushi Takahashi , Toshiyuki Hata , Hiroshi Sato , Keiichi Ookawa
IPC分类号： H01L23/495
CPC分类号： H01L23/49555 , H01L21/4814 , H01L21/56 , H01L21/561 , H01L21/565 , H01L23/28 , H01L23/3107 , H01L23/495 , H01L23/4952 , H01L23/49548 , H01L23/49562 , H01L23/49575 , H01L23/49582 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/81 , H01L24/83 , H01L24/84 , H01L24/97 , H01L29/7833 , H01L2224/0401 , H01L2224/04026 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/16245 , H01L2224/29011 , H01L2224/29015 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40225 , H01L2224/45124 , H01L2224/45139 , H01L2224/73253 , H01L2224/75251 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2224/83101 , H01L2224/83138 , H01L2224/83191 , H01L2224/83825 , H01L2224/8385 , H01L2224/83851 , H01L2224/84801 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01068 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/18301 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H05K3/3426 , H01L2224/81 , H01L2224/83 , H01L2924/00 , H01L2924/01049 , H01L2924/01083 , H01L2224/29139 , H01L2924/3512 , H01L2224/48 , H01L2924/00012
摘要： A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view.
摘要翻译：一种具有半导体芯片的半导体器件，具有第一主表面和第二相对的主表面，并且包括形成在第一主表面上的源极和栅电极的MOSFET，以及形成在第二主表面上的漏电极，第一和第二导电作为源电极和栅电极的引线端子的部件分别设置在第一主表面上，第一和第二导电部件中的每一个在平面图中与芯片重叠，密封体密封芯片和部件的第一和第二导电构件，使得第一导电构件的一部分从密封体的第一侧表面向外突出，并且第一和第二导电构件的部分从密封体的相对的第二侧表面向外突出在平面图中。

67. 发明授权

US08362614B2 Fine pitch grid array type semiconductor device 有权
标题翻译：细间距阵列型半导体器件
公开(公告)号：US08362614B2
公开(公告)日：2013-01-29
申请号：US11247215
申请日：2005-10-12
申请人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
发明人： Mitsuaki Katagiri , Hiroya Shimizu , Fumiyuki Osanai , Yasushi Takahashi , Seiji Narui
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/50 , H01L23/49838 , H01L2224/4824 , H01L2924/13091 , H01L2924/15173 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.
摘要翻译：半导体器件具有其中布置有多个半导体部件和多个焊盘的半导体芯片，布置在栅格中的多个外部连接触点，以及用于电连接焊盘和外部连接触点的多条引线。焊盘包括多个焊盘组，其包括连接到共同的多个半导体部件的一对电极焊盘和分别连接到连接到电极焊盘的半导体部件的多个信号焊盘。在每个焊盘组中，每个信号焊盘被布置成与电极焊盘之一相邻; 并且从每个信号焊盘延伸的每条焊丝沿着与每个信号焊盘相邻的电极焊盘延伸的焊丝延伸。

68. 发明授权

US08274844B2 Semiconductor memory device, information processing system including the same, and controller 有权
标题翻译：半导体存储器件，包括其的信息处理系统和控制器
公开(公告)号：US08274844B2
公开(公告)日：2012-09-25
申请号：US12784147
申请日：2010-05-20
申请人： Yasushi Takahashi , Toru Ishikawa
发明人： Yasushi Takahashi , Toru Ishikawa
IPC分类号： G11C7/00
CPC分类号： G11C11/4096 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
摘要： To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.
摘要翻译：分别包括分配给第一和第二存储器电路单元的第一和第二数据输入/输出端子以及共同分配给这些存储器电路单元的地址端子。当第一芯片选择信号被激活时，与第二存储器电路单元的操作无关地，第一存储器电路单元基于地址信号经由第一数据输入/输出端执行读操作或写操作。当第二芯片选择信号被激活时，第二存储器电路单元基于地址信号执行经由第二数据输入/输出端子的读取操作或写入操作，而与第一存储器电路单元的操作无关。利用这种配置，可以防止浪费的数据传送，并且可以提高有效的数据传送速率。

69. 发明授权

US07582884B2 Charged particle beam exposure method and charged particle beam exposure device 失效
标题翻译：带电粒子束曝光方法和带电粒子束曝光装置
公开(公告)号：US07582884B2
公开(公告)日：2009-09-01
申请号：US11104444
申请日：2005-04-13
申请人： Yasushi Takahashi
发明人： Yasushi Takahashi
IPC分类号： G21K5/10 , H01J37/08
CPC分类号： H01J37/3174 , B82Y10/00 , B82Y40/00 , H01J2237/31776
摘要： When a space, sandwiched by large patterns having a predetermined size or more, is exposed using a charged particle beam, the space sandwiched by the large patterns is exposed using a common block mask having the space and edge portions of the large patterns on both sides of the space, and portions other than the edge portions of the large patterns on both sides are exposed by a variable rectangular beam or by using another block mask.
摘要翻译：当使用具有预定尺寸或更大尺寸的大图案夹持的空间使用带电粒子束曝光时，使用具有两侧的大图案的空间和边缘部分的公共阻挡掩模来曝光由大图案夹持的空间并且两侧的大图案的边缘部分之外的部分通过可变的矩形光束或通过使用另一个块掩模曝光。

70. 外观设计

USD598991S1 Lavatory 有权
公开(公告)号：USD598991S1
公开(公告)日：2009-08-25
申请号：US29326388
申请日：2008-10-16
申请人： Yasushi Takahashi , Mitsuya Obara , Masahiro Maruhashi
设计人： Yasushi Takahashi , Mitsuya Obara , Masahiro Maruhashi

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