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61. 发明授权

US06984547B2 Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation 失效
标题翻译：非接触均匀隧道分离p-well（尖点）非易失性存储器阵列架构，制造和操作
公开(公告)号：US06984547B2
公开(公告)日：2006-01-10
申请号：US10662074
申请日：2003-09-12
申请人： Chun Chen , Andrei Mihnea , Kirk Prall
发明人： Chun Chen , Andrei Mihnea , Kirk Prall
IPC分类号： H01L21/82
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.
摘要翻译：在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。这种浮栅存储器单元的列与包含列中的每个存储器单元的源/漏区的阱相关联。这些阱与阵列的其他列的源/漏区隔离。可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

62. 发明申请

US20050173754A1 Method and apparatus for a flash memory device comprising a source local interconnect 失效
标题翻译：一种用于包括源局部互连的闪存器件的方法和装置
公开(公告)号：US20050173754A1
公开(公告)日：2005-08-11
申请号：US11105834
申请日：2005-04-14
申请人： Kirk Prall , Chun Chen
发明人： Kirk Prall , Chun Chen
IPC分类号： H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/082 , H01L27/102 , H01L27/115 , H01L29/70 , H01L29/76 , H01L29/788 , H01L31/062 , H01L31/11
CPC分类号： H01L27/11521 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/115
摘要： A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.
摘要翻译：用于形成具有连接在扇区内的多个晶体管的源极区域的局部互连的快闪存储器件的方法允许覆盖源极区域的电介质区域的高度选择性的湿蚀刻。该方法的一个实施例包括使用覆盖各种特征的耐蚀刻层，例如在源极区域上残留的任何栅极氧化物，沿着晶体管叠层的侧壁的间隔物，以及晶体管的覆盖层。还公开了由本发明方法得到的过程中半导体器件。

63. 发明申请

US20050122787A1 Memory transistor and methods 有权
标题翻译：存储晶体管及方法
公开(公告)号：US20050122787A1
公开(公告)日：2005-06-09
申请号：US11023719
申请日：2004-12-28
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L21/28 , H01L29/78 , H01L29/792 , G11C5/00
CPC分类号： H01L29/0847 , H01L21/28273 , H01L21/28282 , H01L29/66643 , H01L29/7839 , H01L29/7885 , H01L29/792
摘要： A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.
摘要翻译：形成存储晶体管的方法包括提供包括半导体材料并形成间隔开的源极/漏极结构的衬底。源极/漏极结构中的至少一个与半导体材料形成肖特基接触。该方法还包括在间隔开的源极/漏极结构之间形成存储栅极，并形成可操作地设置在存储器栅极上的控制栅极。

64. 发明申请

US20050078521A1 Programming methods for multi-level flash EEPROMs 失效
标题翻译：多级闪存EEPROM的编程方法
公开(公告)号：US20050078521A1
公开(公告)日：2005-04-14
申请号：US10999030
申请日：2004-11-29
申请人： Chun Chen , Kirk Prall
发明人： Chun Chen , Kirk Prall
IPC分类号： G11C7/00 , G11C11/34 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.
摘要翻译：提供了一种用于对电可擦除可编程只读存储器的存储单元进行编程的方法。存储单元制造在衬底上，并且包括源极区域，漏极区域，浮动栅极和控制栅极。存储单元具有可选地配置为至少三个编程状态之一的阈值电压。该方法包括通过在漏极区域和源极区域之间施加漏极 - 源极偏置电压来在漏极区域和源极区域之间产生漏极电流。该方法还包括通过向控制栅极施加栅极电压将热电子从漏极电流注入到浮置栅极。通过施加选定的恒定漏极 - 源极偏置电压和所选择的栅极电压来产生对应于所选择的一个编程状态的存储单元的选定阈值电压。

65. 发明授权

US06649453B1 Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation 失效
标题翻译：非接触均匀隧道分离p-well（CUSP）非易失性存储器阵列架构，制造和操作
公开(公告)号：US06649453B1
公开(公告)日：2003-11-18
申请号：US10230597
申请日：2002-08-29
申请人： Chun Chen , Andrei Mihnea , Kirk Prall
发明人： Chun Chen , Andrei Mihnea , Kirk Prall
IPC分类号： H01L2182
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.
摘要翻译：在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。这些阱与阵列的其他列的源/漏区隔离。可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

66. 发明授权

US06586304B2 SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS 失效
公开(公告)号：US06586304B2
公开(公告)日：2003-07-01
申请号：US08881852
申请日：1997-06-24
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L21336
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78642 , Y10S257/905
摘要： The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes, a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact. In still another aspect, a DRAM array of memory cells comprises a plurality of wordlines, source regions, drain regions, bit lines in electrical connection with the drain regions, and storage capacitors in electrical connection with the source regions; at least two drain regions of different memory cells being interconnected with one another beneath one of the wordlines. In yet another aspect, a DRAM array has more than two memory cells for a single bit line contact, and a plurality of individual memory cells occupy a surface area of less than or equal to 2f×(2f+f/N), where “f” is the minimum photolithographic feature size with which the array was fabricated, and “N” is the number of memory cells per single bit line contact within the portion.

67. 发明授权

US06429526B1 Method for forming a semiconductor connection with a top surface having an enlarged recess 有权
公开(公告)号：US06429526B1
公开(公告)日：2002-08-06
申请号：US09310649
申请日：1999-05-12
申请人： Guy Blalock , Kirk Prall , Fernando Gonzalez
发明人： Guy Blalock , Kirk Prall , Fernando Gonzalez
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L23/485 , H01L23/5226 , H01L23/535 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

68. 发明授权

US06404008B1 Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors 有权
标题翻译：采用绝缘体上半导体晶体管的绝缘体上半导体晶体管和存储器电路
公开(公告)号：US06404008B1
公开(公告)日：2002-06-11
申请号：US09315900
申请日：1999-05-20
申请人： Kirk Prall
发明人： Kirk Prall
IPC分类号： H01L27108
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78642 , Y10S257/905
摘要： The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes, a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact. In still another aspect, a DRAM array of memory cells comprises a plurality of wordlines, source regions, drain regions, bit lines in electrical connection with the drain regions, and storage capacitors in electrical connection with the source regions; at least two drain regions of different memory cells being interconnected with one another beneath one of the wordlines. In yet another aspect, a DRAM array has more than two memory cells for a single bit line contact, and a plurality of individual memory cells occupy a surface area of less than or equal to 2f×(2f+f/N), where “f” is the minimum photolithographic feature size with which the array was fabricated, and “N” is the number of memory cells per single bit line contact within the portion.
摘要翻译：本发明包括与绝缘体上半导体晶体管，存储器和其他DRAM电路和阵列到晶体管栅极阵列有关的几个方面，以及制造这种结构的方法。在一个方面，绝缘体上半导体晶体管包括：a）绝缘体层; b）绝缘体层上的半导体材料层; c）设置在半导体材料层内的晶体管栅极; 以及d）设置在半导体材料层内的外部高程源极/漏极扩散区域和内部高程扩散区域，其可操作地接近晶体管栅极。在另一方面，DRAM电路包括不需要顺序访问的多个存储单元，多个存储单元的至少一部分具有用于单位线接触的多于两个存储单元。在另一方面，存储器单元的DRAM阵列包括多个字线，源极区，漏极区，与漏极区电连接的位线以及与源极区域电连接的存储电容器; 不同存储器单元的至少两个漏极区域在一条字线之下彼此互连。在另一方面，DRAM阵列具有用于单个位线接触的多于两个存储单元，并且多个独立存储单元占据小于或等于2fx（2f + f / N）的表面积，其中“f “是制造阵列的最小光刻特征尺寸，”N“是该部分内单个位线接触的存储单元数。

69. 发明授权

US06326250B1 Semiconductor processing method of fabricating field effect transistors 失效
标题翻译：制造场效应晶体管的半导体处理方法
公开(公告)号：US06326250B1
公开(公告)日：2001-12-04
申请号：US08990200
申请日：1997-12-22
申请人： Aftab Ahmad , Kirk Prall
发明人： Aftab Ahmad , Kirk Prall
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/823814
摘要： In one aspect of the invention, a semiconductor processing method includes: a) providing a semiconductor substrate; b) defining a first conductivity type region and a second conductivity type region of the semiconductor substrate; c) providing a first transistor gate over the first type region which defines a first source area and a first drain area operatively adjacent thereto; d) providing a second transistor gate over the second type region which defines a second source area and a second drain area operatively adjacent thereto; and e) blanket implanting a conductivity enhancing dopant of the second conductivity type through the first source and drain areas of the first conductivity region and the second source and drain areas of the second conductivity region to provide second conductivity type regular LDD implant regions within the substrate operatively adjacent the first transistor gate and to provide second conductivity type halo implant regions within the substrate operatively adjacent the second transistor gate. In another aspect, a semiconductor processing method includes: a) providing a semiconductor substrate; b) providing a transistor gate over the semiconductor substrate; c) providing spacers adjacent the transistor gate; d) providing electrically conductive source and drain implant regions within the substrate operatively adjacent the transistor gate; e) implanting a conductivity enhancing dopant into the previously formed electrically conductive source and drain regions; and f) driving the conductivity enhancing dopant under the spacers to form graded junction regions.
摘要翻译：在本发明的一个方面，半导体处理方法包括：a）提供半导体衬底; b）限定半导体衬底的第一导电类型区域和第二导电类型区域; c）在所述第一类型区域上提供限定与其可操作地相邻的第一源区域和第一漏极区域的第一晶体管栅极; d）在所述第二类型区域上提供限定与其可操作地相邻的第二源极区域和第二漏极区域的第二晶体管栅极; 以及e）通过所述第一导电区域的所述第一源极和漏极区域以及所述第二导电区域的所述第二源极和漏极区域覆盖所述第二导电类型的电导率增强掺杂剂，以在所述衬底内提供第二导电类型的常规LDD注入区域可操作地与第一晶体管栅极相邻并且在衬底内提供可操作地邻近第二晶体管栅极的第二导电类型的晕圈注入区域。另一方面，半导体处理方法包括：a）提供半导体衬底; b）在半导体衬底上提供晶体管栅极; c）提供与晶体管栅极相邻的间隔物; d）在所述衬底内提供与所述晶体管栅极可操作地相邻的导电源极和漏极注入区域; e）将电导率增强掺杂剂注入到先前形成的导电源极和漏极区域中; 以及f）在所述间隔物下驱动所述导电性增强掺杂剂以形成渐变连接区域。

70. 发明授权

US06181594B2 Reduced leakage DRAM storage unit 有权
标题翻译：减少漏电DRAM存储单元
公开(公告)号：US06181594B2
公开(公告)日：2001-01-30
申请号：US09426699
申请日：1999-10-25
申请人： Zhiqiang (Jeff) Wu , Randhir P S Thakur , Alan Reinberg , Kirk Prall
发明人： Zhiqiang (Jeff) Wu , Randhir P S Thakur , Alan Reinberg , Kirk Prall
IPC分类号： G11C1134
CPC分类号： H01L27/10808 , G11C11/404 , H01L27/108
摘要： The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.
摘要翻译：本发明涉及一种存储单元，其包括存储节点，用于控制对存储节点的访问的开关装置，以及开关装置与存储节点之间的二极管。还公开了一种用于控制通过开关装置从存储节点传输电荷的方法。

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