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1. 发明授权

US07115509B2 Method for forming polysilicon local interconnects 有权
标题翻译：用于形成多晶硅局部互连的方法
公开(公告)号：US07115509B2
公开(公告)日：2006-10-03
申请号：US10714752
申请日：2003-11-17
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/44
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

2. 发明申请

US20050285148A1 Memory with polysilicon local interconnects 审中-公开
标题翻译：具有多晶硅局部互连的存储器
公开(公告)号：US20050285148A1
公开(公告)日：2005-12-29
申请号：US11217739
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336 , H01L21/768 , H01L21/8247 , H01L23/48 , H01L27/115 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

3. 发明授权

US07696557B2 Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation 失效
标题翻译：非接触均匀隧道分离p-well（CUSP）非易失性存储器阵列架构，制造和操作
公开(公告)号：US07696557B2
公开(公告)日：2010-04-13
申请号：US11706587
申请日：2007-02-15
申请人： Chun Chen , Andrei Mihnea , Kirk Prall
发明人： Chun Chen , Andrei Mihnea , Kirk Prall
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.
摘要翻译：在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。这些阱与阵列的其他列的源/漏区隔离。可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

4. 发明申请

US20070164348A1 Contactless uniform-tunneling separate p-well (cusp)non-volatile memory array architecture, fabrication and operation 失效
标题翻译：非接触均匀隧道分离p-well（尖点）非易失性存储器阵列架构，制造和操作
公开(公告)号：US20070164348A1
公开(公告)日：2007-07-19
申请号：US11706587
申请日：2007-02-15
申请人： Chun Chen , Andrei Mihnea , Kirk Prall
发明人： Chun Chen , Andrei Mihnea , Kirk Prall
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.
摘要翻译：在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。这些阱与阵列的其他列的源/漏区隔离。可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

5. 发明授权

US07199422B2 Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and operation 失效
标题翻译：非接触均匀隧道分离P-well（CUSP）非易失性存储器阵列架构，制造和操作
公开(公告)号：US07199422B2
公开(公告)日：2007-04-03
申请号：US11006177
申请日：2004-12-06
申请人： Chun Chen , Andrei Mihnea , Kirk Prall
发明人： Chun Chen , Andrei Mihnea , Kirk Prall
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.
摘要翻译：在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。这些阱与阵列的其他列的源/漏区隔离。可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

6. 发明申请

US20060009035A1 Method for forming polysilicon local interconnects 审中-公开
公开(公告)号：US20060009035A1
公开(公告)日：2006-01-12
申请号：US11218099
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/44
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

7. 发明申请

US20060008989A1 Method for forming an array with polysilicon local interconnects 有权
公开(公告)号：US20060008989A1
公开(公告)日：2006-01-12
申请号：US11217946
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

8. 发明申请

US20050078529A1 Programming methods for multi-level flash EEPROMs 失效
公开(公告)号：US20050078529A1
公开(公告)日：2005-04-14
申请号：US10998697
申请日：2004-11-29
申请人： Chun Chen , Kirk Prall
发明人： Chun Chen , Kirk Prall
IPC分类号： G11C7/00 , G11C11/34 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483
摘要： A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

9. 发明授权

US07517749B2 Method for forming an array with polysilicon local interconnects 有权
标题翻译：用多晶硅局部互连形成阵列的方法
公开(公告)号：US07517749B2
公开(公告)日：2009-04-14
申请号：US11217946
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

10. 发明申请

US20060008988A1 Method of forming a memory cell 审中-公开
标题翻译：形成存储单元的方法
公开(公告)号：US20060008988A1
公开(公告)日：2006-01-12
申请号：US11217944
申请日：2005-09-01
申请人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
发明人： Chun Chen , Guy Blalock , Graham Wolstenholme , Kirk Prall
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/76895 , H01L27/115
摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.
摘要翻译：描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

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