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61. 发明授权

US07952911B2 SRAM cell array structure 有权
标题翻译： SRAM单元阵列结构
公开(公告)号：US07952911B2
公开(公告)日：2011-05-31
申请号：US12111905
申请日：2008-04-29
申请人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C11/419
摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

62. 发明授权

US07808812B2 Robust 8T SRAM cell 有权
标题翻译：坚固的8T SRAM单元
公开(公告)号：US07808812B2
公开(公告)日：2010-10-05
申请号：US12238850
申请日：2008-09-26
申请人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
发明人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有第一存储节点的一对交叉耦合的反相器，具有连接在第一存储节点和位线之间的源极和漏极的第一NMOS晶体管，第二NMOS晶体管，其源极和漏极连接在第一NMOS晶体管的栅极和字线之间，第二NMOS晶体管具有连接到第一列选择线的栅极和具有源极和漏极的第三NMOS晶体管连接在接地（VSS）和第一NMOS晶体管的栅极之间，以及连接到第二列选择线的栅极，第二列选择线与第一列选择线互补。

63. 发明申请

US20100080045A1 ROBUST 8T SRAM CELL 有权
标题翻译：稳定的8T SRAM单元
公开(公告)号：US20100080045A1
公开(公告)日：2010-04-01
申请号：US12238850
申请日：2008-09-26
申请人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
发明人： Jack Liu , Shao-Yu Chou , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： This invention discloses a static random access memory (SRAM) cell which comprises a pair of cross-coupled inverters having a first storage node, a first NMOS transistor having a source and a drain connected between the first storage node and a bit-line, a second NMOS transistor having a source and a drain connected between a gate of the first NMOS transistor and a word-line, the second NMOS transistor having a gate connected to a first column select line, and a third NMOS transistor having a source and a drain connected between a ground (VSS) and the gate of the first NMOS transistor, and a gate connected to a second column select line, the second column select line being complementary to the first column select line.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括具有第一存储节点的一对交叉耦合的反相器，具有连接在第一存储节点和位线之间的源极和漏极的第一NMOS晶体管，第二NMOS晶体管，其源极和漏极连接在第一NMOS晶体管的栅极和字线之间，第二NMOS晶体管具有连接到第一列选择线的栅极和具有源极和漏极的第三NMOS晶体管连接在接地（VSS）和第一NMOS晶体管的栅极之间，以及连接到第二列选择线的栅极，第二列选择线与第一列选择线互补。

64. 发明申请

US20090268501A1 Novel SRAM Cell Array Structure 有权
标题翻译：新型SRAM单元阵列结构
公开(公告)号：US20090268501A1
公开(公告)日：2009-10-29
申请号：US12111905
申请日：2008-04-29
申请人： Cheng-Hung Hung Lee , Ching-Wei Wu , Hung-Jen Liao
发明人： Cheng-Hung Hung Lee , Ching-Wei Wu , Hung-Jen Liao
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C11/419
摘要： This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元阵列结构，其包括耦合到一列SRAM单元的第一和第二位线，第一和第二位线基本上彼此平行并由第一金属层，并且第一导线被放置在第一和第二位线之间并跨越SRAM单元的列而不与其形成导电耦合，第一导电线也由第一金属层形成。

65. 发明授权

US07505345B2 Circuit and method for an SRAM with two phase word line pulse 有权
标题翻译：具有两相字线脉冲的SRAM的电路和方法
公开(公告)号：US07505345B2
公开(公告)日：2009-03-17
申请号：US11811659
申请日：2007-06-11
申请人： Chia Wei Wang , Cheng Hung Lee , Hung-Jen Liao , Fu-Chieh Hsu
发明人： Chia Wei Wang , Cheng Hung Lee , Hung-Jen Liao , Fu-Chieh Hsu
IPC分类号： G11C7/02
CPC分类号： G11C11/418 , G11C8/08
摘要： A circuit and method for providing a two phase word line pulse for use during access cycles in an SRAM memory with improved operating margins. A first and a second timing circuit are provided and a word line voltage suppression circuit is provided to reduce the voltage on the active word lines in a first phase of a word line pulse, and to allow the word lines to rise to a second, unsuppressed voltage in a second phase of the word line pulse, responsive to the first and second timing circuits. The first and second timing circuits observe the bit lines voltage discharge and provide control signals active when the bit lines are discharged past certain thresholds, these signals control the voltage suppression circuit. Operating margins for the SRAM are therefore improved. Methods for operating an SRAM using a two phase word line pulse are provided.
摘要翻译：一种电路和方法，用于在具有改进的操作余量的SRAM存储器中的访问周期期间提供两相字线脉冲。提供第一和第二定时电路，并且提供字线电压抑制电路以减小字线脉冲的第一相中有效字线上的电压，并允许字线上升到第二，未压缩响应于第一和第二定时电路在字线脉冲的第二相位中的电压。第一和第二定时电路观察位线电压放电，并且当位线经过某些阈值时提供控制信号有效，这些信号控制电压抑制电路。因此，SRAM的工作裕度得到改善。提供了使用两相字线脉冲来操作SRAM的方法。

66. 发明授权

US07502277B2 Word-line driver design for pseudo two-port memories 有权
标题翻译：用于伪双端口存储器的字线驱动程序设计
公开(公告)号：US07502277B2
公开(公告)日：2009-03-10
申请号：US11599934
申请日：2006-11-15
申请人： Ching-Wei Wu , Cheng Hung Lee , Hung-Jen Liao
发明人： Ching-Wei Wu , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C8/08
摘要： This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.
摘要翻译：本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。

67. 发明授权

US07436696B2 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US07436696B2
公开(公告)日：2008-10-14
申请号：US11582116
申请日：2006-10-17
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an α ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a β ratio of between about 1.45 and 5.
摘要翻译：读优选SRAM单元包括具有第一驱动电流的上拉MOS器件，耦合到上拉MOS器件的下拉MOS器件，具有第二驱动电流的下拉MOS器件，栅极MOS器件具有耦合到上拉MOS器件和下拉MOS器件的第三驱动电流。第一驱动电流和第三驱动电流优选地具有在约0.5和约1之间的α比率。第二驱动电流和第三驱动电流优选具有在约1.45和5之间的β比率。

68. 发明授权

US07394637B2 Sense amplifier with leakage compensation for electrical fuses 有权
标题翻译：带有漏电补偿功能的感应放大器
公开(公告)号：US07394637B2
公开(公告)日：2008-07-01
申请号：US11304174
申请日：2005-12-15
申请人： Sung-Chieh Lin , Hung-Jen Liao , Fu-Lung Hsueh , Jiann-Tseng Huang
发明人： Sung-Chieh Lin , Hung-Jen Liao , Fu-Lung Hsueh , Jiann-Tseng Huang
IPC分类号： H02H5/04
CPC分类号： G11C17/18
摘要： A sense amplifier for detecting a logic state of a selected electrical fuse cell among a number of unselected electrical fuse cells includes a bias module coupled to a power supply for generating a first current, and a tracking module coupled to the bias module for generating a second current. A current supplier is coupled to the bias module and the tracking module for generating a third current substantially equal to a sum of the first and second currents scaled by a predetermined factor, the third current being diverted into a first sub-current flowing through the selected electrical fuse cell and a second sub-current leaking through the unselected electrical fuse cells. The tracking module is so configured that the second current scaled by the predetermined factor is substantially equal to the second sub-current, thereby avoiding the first sub-current to be reduced by the second sub-current.
摘要翻译：用于检测多个未选择的电熔丝单元中的所选择的电熔丝单元的逻辑状态的读出放大器包括耦合到电源的用于产生第一电流的偏置模块，以及耦合到偏置模块的跟踪模块，用于产生第二当前。当前供应商耦合到偏置模块和跟踪模块，用于产生基本上等于由预定因子缩放的第一和第二电流之和的第三电流，第三电流被转移到流过所选择的第一电流的第一子电流电熔丝单元和第二子电流通过未选择的电熔丝单元泄漏。跟踪模块被配置为使得按预定因子缩放的第二电流基本上等于第二子电流，从而避免第一子电流被第二子电流减小。

69. 发明申请

US20080112213A1 Novel word-line driver design for pseudo two-port memories 有权
标题翻译：用于伪双端口存储器的新型字线驱动程序设计
公开(公告)号：US20080112213A1
公开(公告)日：2008-05-15
申请号：US11599934
申请日：2006-11-15
申请人： Ching-Wei Wu , Cheng Hung Lee , Hung-Jen Liao
发明人： Ching-Wei Wu , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C11/00 , G11C7/12 , G11C8/00
CPC分类号： G11C11/412 , G11C8/08
摘要： This invention discloses an integrated circuit, which comprises a first and a second pull-down circuit controlled by a first and second signal, respectively, and coupled between a first node and a low voltage power supply (Vss), and a controllable pull-up circuit coupled between the first node and a complimentary high voltage power supply (Vcc), wherein when either the first or second signal is asserted to a predetermined logic state, the first node is pulled down to a logic LOW state.
摘要翻译：本发明公开了一种集成电路，其包括分别由第一和第二信号控制并耦合在第一节点和低电压电源（Vss）之间的第一和第二下拉电路以及可控上拉耦合在第一节点和互补高压电源（Vcc）之间的电路，其中当第一或第二信号被确定到预定逻辑状态时，第一节点被下拉到逻辑低电平状态。

70. 发明申请

US20080112212A1 Circuits for improving read and write margins in multi-port SRAMS 有权
标题翻译：用于提高多端口SRAMS中读写余量的电路
公开(公告)号：US20080112212A1
公开(公告)日：2008-05-15
申请号：US11598385
申请日：2006-11-13
申请人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jun-Jen Wu , Chen Yen-Huei
发明人： Dao-Ping Wang , Hung-Jen Liao , Kun Lung Chen , Yung-Lung Lin , Jun-Jen Wu , Chen Yen-Huei
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/08 , G11C11/413 , G11C11/418
摘要： A system and method for writing a SRAM cell coupled to complimentary first and second bit-lines (BLs) is disclosed, the method comprising asserting a word-line (WL) selecting the SRAM cell to a first positive voltage, providing a second positive voltage at the first BL, providing a first negative voltage at the second BL, and asserting a plurality of WLs not selecting the SRAM cell to a second negative voltage, wherein the writing margin of the SRAM cell is increased.
摘要翻译：公开了一种用于写入耦合到互补的第一和第二位线（BL）的SRAM单元的系统和方法，所述方法包括断言将SRAM单元选择为第一正电压的字线（WL），提供第二正电压在第一BL处，在第二BL处提供第一负电压，并且将不选择SRAM单元的多个WL确定为第二负电压，其中增加了SRAM单元的写入裕度。

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