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    • 61. 发明授权
    • Apparatus and method for virtualizing interrupts in a logically partitioned computer system
    • 用于虚拟化逻辑分区计算机系统中的中断的装置和方法
    • US07000051B2
    • 2006-02-14
    • US10403158
    • 2003-03-31
    • William Joseph ArmstrongRichard Louis ArndtNaresh Nayar
    • William Joseph ArmstrongRichard Louis ArndtNaresh Nayar
    • G06F13/24G06F9/45
    • G06F13/24G06F9/45541G06F9/4812G06F9/5077
    • A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.
    • 资源和分区管理器以不干扰在逻辑分区上运行的操作系统的中断处理模型的方式,虚拟化中断而不使用任何附加硬件。 换句话说,资源和分区管理器支持逻辑分区的计算机系统中的虚拟中断,其可以包括共享处理器,而不改变逻辑分区的操作系统。 为系统中的每个虚拟处理器创建一组虚拟中断寄存器。 资源和分区管理器使用虚拟中断寄存器来处理相应虚拟处理器的中断。 以这种方式,从操作系统的观点来看,当操作系统在可能包含共享处理器和虚拟中断的逻辑分区中运行时的中断处理与操作系统在计算机中运行时的中断处理没有区别 只包含专用处理器分区的系统。
    • 62. 发明申请
    • Translation look-aside buffer sharing among logical partitions
    • 逻辑分区之间的翻译后备缓冲区共享
    • US20050027960A1
    • 2005-02-03
    • US10631535
    • 2003-07-31
    • Jonathan DeMentCathy MayNaresh NayarEdward Silha
    • Jonathan DeMentCathy MayNaresh NayarEdward Silha
    • G06F12/08G06F12/10
    • G06F12/1036G06F2212/152
    • The present invention provides for storing and using a stored logical partition indicia in a TLB. A partition in a microprocessor architecture is employed. A virtual page number is selected. A stored LPID indicia corresponding to the selected page number is read from a TLB. The stored logical partition indicia from the TLB is compared to a logical partition indicia associated with the employed partition. If the stored logical partition indicia and the logical partition indicia associated with the employed partition match, a corresponding page table entry stored in the translation look-aside buffer is read. If they do not match, a page table entry from a page table entry source is retrieved and stored in the TLB. If a partition is to invalidate an entry in the TLB, a TLB entry command is generated and used to invalidate a memory entry.
    • 本发明提供了在TLB中存储和使用存储的逻辑分区标记。 采用微处理器架构中的分区。 选择虚拟页码。 从TLB中读取对应于所选页码的存储的LPID标记。 将来自TLB的存储的逻辑分区标记与与所使用的分区相关联的逻辑分区标记进行比较。 如果所存储的逻辑分区标记和与所采用分区相关联的逻辑分区标记匹配,则读取存储在转换后备缓冲器中的相应页表条目。 如果它们不匹配,则从页表入口源中的页表项被检索并存储在TLB中。 如果分区要使TLB中的条目无效,则会生成TLB条目命令,并将其用于使内存条目无效。
    • 65. 发明授权
    • Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core
    • 提供逻辑分支与反映独家使用处理器核心的硬件线程特定信息
    • US09069598B2
    • 2015-06-30
    • US13345002
    • 2012-01-06
    • Giles R. FrazierBruce MealyNaresh Nayar
    • Giles R. FrazierBruce MealyNaresh Nayar
    • G06F9/455G06F9/38
    • G06F21/6218G06F9/3012G06F9/3851G06F9/45541G06F9/45558G06F2009/45587
    • Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
    • 用于模拟在多个逻辑分区(LPAR)中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息,所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器 信息。 如果请求者是在低于管理程序权限级别的特权级别下执行的程序,则转换响应于访问请求而返回的信息,使得每个逻辑分区将处理器视为处理器的独占使用。 这些技术可以由处理器核心内的逻辑电路块来实现,其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示,或者可以通过将访问陷阱的中断处理程序的程序指令执行 物理寄存器包含信息。
    • 67. 发明授权
    • Efficient support of multiple page size segments
    • 高效地支持多个页面大小的段
    • US08862859B2
    • 2014-10-14
    • US12775652
    • 2010-05-07
    • Miles R. DooleySundeep ChadhaNaresh NayarRandal C. Swanberg
    • Miles R. DooleySundeep ChadhaNaresh NayarRandal C. Swanberg
    • G06F12/10
    • G06F12/1027G06F2212/652
    • An apparatus, system, and method are disclosed for improved support of MPS segments in a microprocessor. The virtual address is used to generate possible TLB index values for each of the supported page sizes of the MPS segment associated with the virtual address. The possible TLB index values may be a hash generated using the virtual address and one of the supported page sizes. The TLB is searched for actual TLB index values that match the possible TLB index values calculated using the different supported page sizes. TLB entries associated with those actual TLB index values are checked to determine whether any TLB entry is associated with the virtual address. If no match is found, the real address is retrieved from the PT. The actual page size in the PT is used to generate an actual TLB index value for the virtual address and the TLB entry is inserted into the TLB.
    • 公开了一种用于改进对微处理器中的MPS段的支持的装置,系统和方法。 虚拟地址用于为与虚拟地址相关联的MPS段的每个支持的页面大小生成可能的TLB索引值。 可能的TLB索引值可以是使用虚拟地址和支持的页面大小之一生成的哈希值。 搜索与使用不同的支持的页面大小计算的可能的TLB索引值相匹配的实际TLB索引值的TLB。 检查与这些实际TLB索引值相关联的TLB条目以确定是否有任何TLB条目与虚拟地址相关联。 如果没有找到匹配,则从PT检索真实地址。 PT中的实际页面大小用于生成虚拟地址的实际TLB索引值,并将TLB条目插入到TLB中。
    • 69. 发明授权
    • Privilege level aware processor hardware resource management facility
    • 特权级别的处理器硬件资源管理工具
    • US08695010B2
    • 2014-04-08
    • US13251879
    • 2011-10-03
    • Giles R. FrazierMichael K. GschwindNaresh Nayar
    • Giles R. FrazierMichael K. GschwindNaresh Nayar
    • G06F9/46
    • G06F9/45533G06F9/45558G06F9/462G06F9/5077G06F2009/45579
    • Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.
    • 多个机器状态寄存器被包括在处理器核心中,以便区分应用程序,监督线程和管理程序之间的硬件设施的使用。 当初始化分区时,所有的设备最初被管理程序禁用。 当对残疾设施进行访问时,管理程序将收到访问哪个设施的指示,并在管理程序的机器状态寄存器中设置相应的硬件标志。 当应用程序尝试访问禁用的设备时,管理操作系统映像的主管接收到哪个设备被访问的指示,并在主管机器状态寄存器中设置相应的硬件标志。 多寄存器实现允许主管当发生应用程序上下文交换时确定特定硬件设施是否需要保存其状态,并且管理程序可以确定在发生分区交换时哪些硬件设施需要保存其状态。