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1. 发明申请

US20050027960A1 Translation look-aside buffer sharing among logical partitions 审中-公开
标题翻译：逻辑分区之间的翻译后备缓冲区共享
公开(公告)号：US20050027960A1
公开(公告)日：2005-02-03
申请号：US10631535
申请日：2003-07-31
申请人： Jonathan DeMent , Cathy May , Naresh Nayar , Edward Silha
发明人： Jonathan DeMent , Cathy May , Naresh Nayar , Edward Silha
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1036 , G06F2212/152
摘要： The present invention provides for storing and using a stored logical partition indicia in a TLB. A partition in a microprocessor architecture is employed. A virtual page number is selected. A stored LPID indicia corresponding to the selected page number is read from a TLB. The stored logical partition indicia from the TLB is compared to a logical partition indicia associated with the employed partition. If the stored logical partition indicia and the logical partition indicia associated with the employed partition match, a corresponding page table entry stored in the translation look-aside buffer is read. If they do not match, a page table entry from a page table entry source is retrieved and stored in the TLB. If a partition is to invalidate an entry in the TLB, a TLB entry command is generated and used to invalidate a memory entry.
摘要翻译：本发明提供了在TLB中存储和使用存储的逻辑分区标记。采用微处理器架构中的分区。选择虚拟页码。从TLB中读取对应于所选页码的存储的LPID标记。将来自TLB的存储的逻辑分区标记与与所使用的分区相关联的逻辑分区标记进行比较。如果所存储的逻辑分区标记和与所采用分区相关联的逻辑分区标记匹配，则读取存储在转换后备缓冲器中的相应页表条目。如果它们不匹配，则从页表入口源中的页表项被检索并存储在TLB中。如果分区要使TLB中的条目无效，则会生成TLB条目命令，并将其用于使内存条目无效。

2. 发明申请

US20070143565A1 Apparatus and method for selectively invalidating entries in an address translation cache 有权
标题翻译：用于选择性地使地址转换高速缓存中的条目无效的装置和方法
公开(公告)号：US20070143565A1
公开(公告)日：2007-06-21
申请号：US11304136
申请日：2005-12-15
申请人： Michael Corrigan , Paul Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward Silha
发明人： Michael Corrigan , Paul Godtland , Joaquin Hinojosa , Cathy May , Naresh Nayar , Edward Silha
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F12/126 , G06F2212/1016 , G06F2212/683
摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
摘要翻译：一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。

3. 发明申请

US20060179239A1 Data stream prefetching in a microprocessor 失效
标题翻译：数据流在微处理器中预取
公开(公告)号：US20060179239A1
公开(公告)日：2006-08-10
申请号：US11054889
申请日：2005-02-10
申请人： Eric Fluhr , Bradly Frey , John Griswell , Hung Le , Cathy May , Francis O'Connell , Edward Silha , Albert Williams
发明人： Eric Fluhr , Bradly Frey , John Griswell , Hung Le , Cathy May , Francis O'Connell , Edward Silha , Albert Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.
摘要翻译：在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。数据预取请求被分配与数据流以反映确定的数据流的深度。分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。由处理器执行的指令中的预取控制位控制预取硬件配置。

4. 发明申请

US20080091922A1 Data stream prefetching in a microprocessor 失效
公开(公告)号：US20080091922A1
公开(公告)日：2008-04-17
申请号：US11953637
申请日：2007-12-10
申请人： Eric Fluhr , Bradly Frey , John Griswell , Hung Le , Cathy May , Francis O'Connell , Edward Silha , Albert Williams
发明人： Eric Fluhr , Bradly Frey , John Griswell , Hung Le , Cathy May , Francis O'Connell , Edward Silha , Albert Williams
IPC分类号： G06F9/38
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

5. 发明申请

US20060242702A1 Method for fast decryption of processor instructions in an encrypted instruction power architecture 有权
标题翻译：用于在加密的指令电力架构中快速解密处理器指令的方法
公开(公告)号：US20060242702A1
公开(公告)日：2006-10-26
申请号：US11114552
申请日：2005-04-26
申请人： Gordon McIntosh , Edward Silha
发明人： Gordon McIntosh , Edward Silha
IPC分类号： G06F12/14
CPC分类号： G06F21/57 , G06F9/30178 , G06F9/3802 , G06F21/71 , G06F21/72 , G06F21/85
摘要： A method and apparatus are provided for an independent operating system for the prevention of certain classes of computer attacks that have previously not been preventable. Detailed is an effective methodology to implement instruction decryption using the existing instruction set for a processor. Significant hurdles are addressed in the processor architecture so as to limit the impact to processor execution timing. Instruction execution timing is not altered in the processor core. Any additional processing is overlapped into existing operations and, therefore, the impact on processor throughput is minimal.
摘要翻译：提供了一种用于独立操作系统的方法和装置，用于防止以前不可预防的某些类型的计算机攻击。详细说明是使用现有的处理器指令集实现指令解密的有效方法。在处理器架构中解决了重大障碍，以限制对处理器执行时序的影响。处理器内核中的指令执行时序不会改变。任何额外的处理与现有操作重叠，因此对处理器吞吐量的影响是最小的。

6. 发明申请

US20050091476A1 Apparatus for supporting a logically partitioned computer system 失效
标题翻译：用于支持逻辑分区计算机系统的装置
公开(公告)号：US20050091476A1
公开(公告)日：2005-04-28
申请号：US10948776
申请日：2004-09-23
申请人： Richard Doing , Ronald Kalla , Stephen Schwinn , Edward Silha , Kenichi Tsuchiya
发明人： Richard Doing , Ronald Kalla , Stephen Schwinn , Edward Silha , Kenichi Tsuchiya
IPC分类号： G06F9/38 , G06F12/02 , G06F12/10 , G06F12/14 , G06F15/00
CPC分类号： G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/5077 , G06F12/0284 , G06F12/1036 , G06F12/109 , G06F12/1491
摘要： A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions and can dynamically re-allocate resources. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state, and is capable of entering hypervisor state only upon occurrence of certain pre-defined events. A logical partition identifier is stored in a processor register, and can be altered by the processor only when in hypervisor state. Certain bus communications contain a logical partition identifier tag, and the processor ignores such communications if the tag does not match its own logical partition identifier in its register.
摘要翻译：处理器支持包括计算机系统的真实地址空间的硬件资源的逻辑分区。一个超级特权的管理程序称为虚拟机管理程序，可以调节逻辑分区，并可以动态重新分配资源。优选地，处理器支持硬件多线程，每个线程独立地能够处于管理程序，管理程序或问题状态中，并且仅在某些预定义事件发生时能够进入管理程序状态。逻辑分区标识符存储在处理器寄存器中，并且只有处于管理程序状态时才能被处理器改变。某些总线通信包含逻辑分区标识符标签，如果标记与其寄存器中的自己的逻辑分区标识符不匹配，则处理器忽略此类通信。

7. 发明申请

US20050155019A1 Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program 失效
标题翻译：用于在页表中维护性能监视结构以用于监视计算机程序的性能的方法和装置
公开(公告)号：US20050155019A1
公开(公告)日：2005-07-14
申请号：US10757250
申请日：2004-01-14
申请人： Frank Levine , Christopher Richardson , Edward Silha
发明人： Frank Levine , Christopher Richardson , Edward Silha
IPC分类号： G06F9/44 , G06F12/10
CPC分类号： G06F11/3636
摘要： A method and apparatus in a data processing system for measuring events associated with the execution of instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators, counters, thresholds, and other performance monitoring structures may be stored in a page table that is used to translate virtual addresses into physical storage addresses. A standard page table is augmented with additional fields for storing the performance monitoring structures. These structures may be set by the performance monitoring application and may be queried and modified as events occur that require access to physical storage.
摘要翻译：提供了一种用于测量与执行指令相关的事件的数据处理系统中的方法和装置。在数据处理系统的处理器处接收指令。如果所选择的指示符与指令相关联，则启用与执行指令相关联的每个事件的计数。在一些实施例中，可以将性能指示符，计数器，阈值和其他性能监视结构存储在用于将虚拟地址转换为物理存储地址的页表中。标准页表增加了用于存储性能监视结构的附加字段。这些结构可以由性能监视应用程序设置，并且可以在需要访问物理存储的事件发生时进行查询和修改。

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