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61. 发明授权

US06493271B2 Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：US06493271B2
公开(公告)日：2002-12-10
申请号：US09987957
申请日：2001-11-16
申请人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G11C1604
CPC分类号： H01L27/11526 , G06F9/445 , G06F15/7814 , G06F15/7821 , G11C7/1045 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11546 , Y02D10/43
摘要： A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
摘要翻译：具有电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储器单元的可重写非易失性存储器，并且被设置为便于闪存擦除以及多个存储器单元的各个单元的选择性擦除。用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

62. 发明授权

US06377363B1 Image forming apparatus 失效
标题翻译：图像形成装置
公开(公告)号：US06377363B1
公开(公告)日：2002-04-23
申请号：US09276505
申请日：1999-03-25
申请人： Takashi Ito
发明人： Takashi Ito
IPC分类号： H04N132
CPC分类号： H04N1/00912 , G06K15/00 , H04N1/00127 , H04N1/00538 , H04N2201/0036 , H04N2201/0074 , H04N2201/33314 , H04N2201/33328
摘要： An image forming apparatus is composed of an image forming unit and a main controlling unit. The user can combine the image forming unit and main controlling unit of different types having different printing conditions such as image clock frequency, system speed and printing start timing, etc. Information items for determining resolution, image clock frequency, system speed time up to the beam generation timing from the horizontal synchronizing signal, time up to the beam generation timing from the vertical synchronizing signal and number of rotations of an optical beam deflecting device are shared with the main controlling unit and image forming unit through communication.
摘要翻译：图像形成装置由图像形成单元和主控制单元构成。用户可以组合图像形成单元和不同类型的主控制单元，具有不同的打印条件，如图像时钟频率，系统速度和打印开始时间等。用于确定分辨率，图像时钟频率，系统速度时间的信息项目通过通信，与主控制单元和图像形成单元共享来自水平同步信号的波束产生定时，直到来自垂直同步信号的波束产生定时和光束偏转装置的旋转数。

63. 发明授权

US06258283B1 Method of making magnetic resistance element 失效
标题翻译：制造磁阻元件的方法
公开(公告)号：US06258283B1
公开(公告)日：2001-07-10
申请号：US09193425
申请日：1998-11-17
申请人： Masaaki Mikami , Takashi Ito , Takamitsu Orimoto , Mitsumasa Okada
发明人： Masaaki Mikami , Takashi Ito , Takamitsu Orimoto , Mitsumasa Okada
IPC分类号： B44C122
CPC分类号： B82Y25/00 , G01R33/093 , G11B5/3116 , G11B5/3903 , G11B5/3932 , H01L43/12 , Y10T29/49021 , Y10T29/49032 , Y10T29/49046 , Y10T29/49048 , Y10T428/1143
摘要： The method of making the magnetic resistance element comprises the steps of: forming a first magnetizable layer, a non-magnetizable layer and a second magnetizable layer, in this order, on an insulating layer; providing a resist layer for forming a main part of the magnetic resistance element on the second magnetizable layer; etching side faces of the first magnetizable layer, the non-magnetizable layer and the second magnetizable layer to form into slope faces by ion milling from the second magnetizable layer side; forming terminals on the slope faces; and removing the resist layer, wherein a part of the first magnetizable layer which is located outside of the slope faces is left on the insulating layer when the side faces of the first magnetizable layer, the non-magnetizable layer and the second magnetizable layer are etched by ion milling.
摘要翻译：制造磁阻元件的方法包括以下步骤：在绝缘层上依次形成第一可磁化层，不可磁化层和第二可磁化层; 提供用于在所述第二可磁化层上形成所述磁阻元件的主要部分的抗蚀剂层; 蚀刻第一可磁化层，不可磁化层和第二可磁化层的侧面，以从第二可磁化层侧离子铣削形成倾斜面; 在坡面上形成端子; 以及去除所述抗蚀剂层，其中当所述第一可磁化层，所述不可磁化层和所述第二可磁化层的侧面被蚀刻时，位于所述倾斜面外侧的所述第一可磁化层的一部分留在所述绝缘层上通过离子研磨。

64. 发明授权

US6050406A Storage case for diffraction grating 失效
$Storage case for diffraction grating$
标题翻译：衍射光栅的储存盒
公开(公告)号：US6050406A
公开(公告)日：2000-04-18
申请号：US120463
申请日：1998-07-23
申请人： Yoshimitsu Nomura , Masaaki Fukuda , Takashi Ito , Kaneyoshi Yagi
发明人： Yoshimitsu Nomura , Masaaki Fukuda , Takashi Ito , Kaneyoshi Yagi
IPC分类号： G02B5/18 , B65D21/02 , B65D71/70 , B65D85/38
CPC分类号： B65D71/70 , B65D21/0213
摘要： Provided is a storage case for a diffraction grating, which accommodates the diffraction grating in a constant orientation, so as to improve efficiency in the operation for assembling the diffraction grating. The storage sections each accommodate a diffraction grating Each storage section forms a storage space for accommodating a diffraction grating. The storage space is equipped with a rib for engaging the outer peripheral portion of the diffraction grating.
摘要翻译：提供了一种用于衍射光栅的存储盒，其以恒定的方向容纳衍射光栅，以提高组装衍射光栅的操作的效率。存储部分各自容纳衍射光栅每个存储部分形成用于容纳衍射光栅的存储空间。存储空间配备有用于接合衍射光栅的外周部的肋。

65. 发明授权

US6026020A Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：US6026020A
公开(公告)日：2000-02-15
申请号：US788198
申请日：1997-01-24
申请人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G06F9/445 , G06F15/78 , G11C7/10 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11526 , G06F15/7814 , G06F15/7821 , G06F9/445 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C7/1045 , H01L27/115 , H01L27/11531 , H01L27/11546 , H01L27/105 , Y02B60/185
摘要： A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory blocks each of which has a plurality of electrically programmable nonvolatile memory cells arranged in rows and columns in which each nonvolatile memory cell is coupled to one of a plurality of word lines and one of a plurality of data lines of the flash memory. The memory blocks formed can be facilitated with different memory capacities, including through controlling the number of rows or columns of memory cells associated therewith. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage from a corresponding one of plural source voltage control circuits, for flash erasing the memory cells in that memory block in an erasing operation. In accordance with another feature of the flash memory, a control register, included within a device and under the control of the CPU, is employed to control the erasing of data stored in one or more of the memory blocks, simultaneously.
摘要翻译：具有中央处理单元（CPU）和闪速存储器的单芯片半导体集成电路器件，其存储要由CPU处理的数据，并且响应于通过地址访问来自CPU的指令，通过数据总线向CPU提供数据总线。闪存由多个存储块构成，每个存储块具有排列成行和列的多个电可编程非易失性存储单元，其中每个非易失性存储单元耦合到多个字线中的一个，多个字线中的一个数据线的闪存。所形成的存储器块可以通过不同的存储器容量来实现，包括通过控制与其相关联的存储器单元的行数或列数来实现。每个存储块内的所有存储单元的源极连接到单个源极线，该源极线由多个源极电压控制电路中相应的一个源极电压控制电路的预定电压馈送，用于在擦除操作中闪存该存储器块中的存储器单元。根据闪速存储器的另一特征，使用包括在设备内并在CPU的控制下的控制寄存器来同时控制存储在一个或多个存储器块中的数据的擦除。

66. 发明授权

US6008957A Optical lens and method of making the same 失效
标题翻译：光学透镜及其制作方法
公开(公告)号：US6008957A
公开(公告)日：1999-12-28
申请号：US154749
申请日：1998-09-17
申请人： Yoshimitsu Nomura , Masaaki Fukuda , Takashi Ito , Kaneyoshi Yagi
发明人： Yoshimitsu Nomura , Masaaki Fukuda , Takashi Ito , Kaneyoshi Yagi
IPC分类号： G02B3/00 , B29D11/00 , G02B3/02 , G11B7/135 , G11B7/22 , G02B7/02
CPC分类号： G11B7/1372 , G02B3/02 , G11B7/22
摘要： A lens includes a center-of-gravity adjusting section in order to prevent the center of gravity of the lens from shifting due to removal of a gate portion formed during molding, thereby providing an optical lens which is easily handled and a method of making the optical lens. An optical lens having a flange at the outer periphery of an optically functioning portion includes a gate-cut section formed by cutting off a part of the flange together with a gate portion, continuously with the flange, and a center-of-axis adjusting section, formed by removing a part of the flange, for positioning the center of gravity in alignment with the optical axis of the optically functioning portion.
摘要翻译：透镜包括重心调节部分，以便防止透镜的重心由于在模制过程中形成的门部分的移除而移动，从而提供易于处理的光学透镜以及使光学透镜。在光学功能部分的外周具有凸缘的光学透镜包括通过与凸缘连续地切断凸缘的一部分与栅极部分一起形成的切割部分和轴向中心调节部分通过去除凸缘的一部分而形成，用于将重心定位成与光学功能部分的光轴对齐。

67. 发明授权

US5967128A Ignition apparatus for an internal combustion engine 失效
标题翻译：内燃机点火装置
公开(公告)号：US5967128A
公开(公告)日：1999-10-19
申请号：US83139
申请日：1998-05-22
申请人： Hiroshi Onuki , Takashi Ito , Katsuaki Fukatsu , Ryoichi Kobayashi , Noboru Sugiura
发明人： Hiroshi Onuki , Takashi Ito , Katsuaki Fukatsu , Ryoichi Kobayashi , Noboru Sugiura
IPC分类号： F02P3/055 , H01F38/12 , H03K17/16 , H03K17/56 , F02P3/05
CPC分类号： F02P3/0554
摘要： According to the invention, a primary winding of an ignition coil is coupled with an insulated-gate bipolar transistor (IGBT). The IGBT is controlled by a current restriction circuit, which includes a control transistor for performing the on-off operation of the IGBT such that the IGBT is made conductive upon occurrence of an ignition control signal, and nonconductive, when a primary current of the ignition coil reaches a certain value depending on a reference voltage determined by a bias circuit. The bias circuit has a condenser, which is charged by a base current of the control transistor to change the base potential of the transistor slowly, when the transistor is made nonconductive.
摘要翻译：根据本发明，点火线圈的初级绕组与绝缘栅双极晶体管（IGBT）耦合。 IGBT由电流限制电路控制，该电流限制电路包括用于执行IGBT的开关操作的控制晶体管，使得当点火控制信号发生时IGBT是导通的，并且在点火的初级电流时导通线圈根据由偏置电路确定的参考电压达到一定值。偏置电路具有电容器，当晶体管不导通时，电容器被控制晶体管的基极电流充电以缓慢地改变晶体管的基极电位。

68. 发明授权

US5915316A Embroidering and laser processing machine 失效
标题翻译：刺绣和激光加工机
公开(公告)号：US5915316A
公开(公告)日：1999-06-29
申请号：US702560
申请日：1996-09-11
申请人： Ikuo Tajima , Takashi Ito , Takashi Shibata
发明人： Ikuo Tajima , Takashi Ito , Takashi Shibata
IPC分类号： B23K26/04 , B23K26/06 , B23K26/067 , B23K26/08 , B23K26/14 , B23K26/42 , D05B37/00 , D05B37/10 , D05C7/10 , D05B21/00
CPC分类号： B23K26/0093 , B23K26/04 , B23K26/064 , B23K26/0648 , B23K26/0665 , B23K26/067 , B23K26/0673 , B23K26/0853 , B23K26/142 , B23K26/1462 , B23K26/402 , B23K26/702 , D05B37/00 , D05B37/10 , D05C7/10 , B23K2201/16 , B23K2201/18 , B23K2203/38
摘要： An embroidering and laser processing machine including at least one sewing head, one laser head and one laser generator, a work holder mounted on a machine table capable of movement in an X-axis and Y-axis direction according to predetermined movement data, the laser generator being on-off controlled according to laser cut codes which are included in the predetermined movement data.
摘要翻译： PCT No.PCT / JP96 / 00047 Sec。 371日期：1996年9月11日 102（e）1996年9月11日PCT PCT 1996年1月11日PCT公布。出版物WO96 / 21534 PCT 日期：1994年7月18日具有至少一个缝纫头，一个激光头和一个激光发生器的刺绣和激光加工机，安装在能够根据预定的X轴和Y轴方向移动的机台上的工件座运动数据，激光发生器根据包括在预定移动数据中的激光切割代码进行开关控制。

69. 发明授权

US5846448A Ferrite and ferrite core for power supply 失效
标题翻译：铁氧体和铁氧体磁芯供电
公开(公告)号：US5846448A
公开(公告)日：1998-12-08
申请号：US564265
申请日：1995-12-27
申请人： Katsushi Yasuhara , Takashi Ito , Osamu Takeda , Shoji Inoue
发明人： Katsushi Yasuhara , Takashi Ito , Osamu Takeda , Shoji Inoue
IPC分类号： C01G49/00 , C04B35/26 , H01F1/34 , C04B35/38
CPC分类号： H01F1/344 , C01G49/009 , C04B35/2658 , C01P2002/32 , C01P2002/52 , C01P2004/02 , C01P2004/61 , C01P2006/42
摘要： A ferrite having low power losses, high .DELTA.B=Bm-Br at high frequency, and improved .mu.a-B properties is provided as well as a core for a power supply using the same. The ferrite contains 30-41 mol % of MnO, 6-16 mol % of ZnO, and the balance of Fe.sub.2 O.sub.3 as main components and 50-250 ppm of SiO.sub.2, 200-1500 ppm of CaO, up to 4000 ppm of SnO.sub.2, up to 3000 ppm of TiO.sub.2, at least 300 ppm of SnO.sub.2 +TiO.sub.2, from more than 0 to 500 ppm of Nb.sub.2 O.sub.5, and from more than 0 to 400 ppm of ZrO.sub.2 as subordinate components.
摘要翻译： PCT No.PCT / JP94 / 00712 Sec。 371 1995年12月27日第 102（e）日期1995年12月27日PCT 1994年4月27日PCT PCT。 WO95 / 29491 PCT出版物日期：1995年11月2日提供了具有低功率损耗的铁氧体，高频率的高DELTA B = Bm-Br，以及改善的μa-B性质，以及使用该铁氧体的电源。铁素体含有30-41mol％的MnO，6-16mol％的ZnO，余量的Fe2O3作为主要成分，50-250ppm的SiO 2，200-1500ppm的CaO，高达4000ppm的SnO 2，至3000ppm的TiO 2，至少300ppm的SnO 2 + TiO 2，超过0至500ppm的Nb 2 O 5和大于0至400ppm的作为下属成分的ZrO 2。

70. 发明授权

US5768194A Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein 失效
标题翻译：数据线无干扰存储器块分割闪存和其中具有闪存的微型计算机
公开(公告)号：US5768194A
公开(公告)日：1998-06-16
申请号：US473114
申请日：1995-06-07
申请人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
发明人： Kiyoshi Matsubara , Naoki Yashiki , Shiro Baba , Takashi Ito , Hirofumi Mukai , Masanao Sato , Masaaki Terasawa , Kenichi Kuroda , Kazuyoshi Shiba
IPC分类号： G06F9/445 , G06F15/78 , G11C7/10 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/30 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C11/34
CPC分类号： H01L27/11526 , G06F15/7814 , G06F15/7821 , G06F9/445 , G11C16/0416 , G11C16/102 , G11C16/105 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3418 , G11C16/3427 , G11C16/3445 , G11C16/3459 , G11C7/1045 , H01L27/115 , H01L27/11531 , H01L27/11546 , H01L27/105 , Y02B60/185
摘要： A single chip semiconductor integrated circuit device having a central processing unit (CPU) and a flash memory which stores data to be processed by the CPU and which provides data to the CPU through the data bus in response to accessing instructions from the CPU through the address bus. The flash memory is constituted by a plurality of memory arrays in which a plurality of word lines are commonly employed for all of the memory arrays and a plurality of data lines are distributed amongst the memory arrays. The nonvolatile memory cells are arranged in a manner in which plural memory blocks are formed. The memory blocks formed can be facilitated with different memory capacities. This is achieved by having one or more rows of memory cells associated with one or more word lines provided within a memory block. Sources of all of the memory cells within each memory block are connected to a single source line which is fed by a predetermined voltage for effecting simultaneous erasure of the memory cells therein from a corresponding one of plural source voltage control circuits. In accordance with another feature of the flash memory, individual ones of plural bit data are assigned to respective ones of the plural memory arrays.
摘要翻译：具有中央处理单元（CPU）和闪速存储器的单芯片半导体集成电路器件，其存储要由CPU处理的数据，并且响应于通过地址访问来自CPU的指令，通过数据总线向CPU提供数据总线。闪存由多个存储器阵列构成，其中多个字线通常用于所有存储器阵列，并且多个数据线分布在存储器阵列之间。以形成多个存储块的方式配置非易失性存储单元。形成的存储块可以利用不同的存储容量来促进。这通过使一行或多行存储器单元与提供在存储器块中的一个或多个字线相关联来实现。每个存储器块内的所有存储单元的源连接到由预定电压馈送的单个源极线，用于从多个源极电压控制电路中相应的一个同时擦除存储器单元。根据闪存的另一特征，将多个位数据中的各个数据分配给多个存储器阵列中的相应的数据。

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