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61. 发明授权

US06471501B1 Mold for fabricating semiconductor devices 有权
标题翻译：用于制造半导体器件的模具
公开(公告)号：US06471501B1
公开(公告)日：2002-10-29
申请号：US09272754
申请日：1999-03-18
申请人： Yasuhiro Shinma , Muneharu Morioka , Norio Fukasawa , Yuzo Hamanaka , Tadashi Uno , Hirohisa Matsuki , Kenichi Nagashige
发明人： Yasuhiro Shinma , Muneharu Morioka , Norio Fukasawa , Yuzo Hamanaka , Tadashi Uno , Hirohisa Matsuki , Kenichi Nagashige
IPC分类号： B29C4514
CPC分类号： B29C43/36 , B29C43/18 , B29C2043/5858 , H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： A mold for press-molding a resin package body includes a lower mold and an upper mold, wherein the upper mold includes a press plate held in a tiltable manner with respect to a press head used for urging the upper mold against the lower mold and a lock mechanism for locking the press plate. The lower mold includes an inner die carrying a semiconductor device and a resin tablet and an outer die surrounding the inner die in a manner movable up and down with respect to the inner die. In operation, the press plate is first engaged with the outer die in the unlocked state to achieve an exact parallelism with respect to the inner die, and after locking the press plate and melting the resin tablet, the press plate is urged further toward the inner die while simultaneously lowering the outer die such that the space formed by the lower die, outer die and the press plate for accommodating a semiconductor chip is collapsed.
摘要翻译：一种用于模制树脂封装体的模具包括下模具和上模具，其中上模具包括相对于用于将上模压靠在下模上的压头可倾斜地保持的压板，以及用于锁定压板的锁定机构。下模包括以相对于内模上下移动的方式承载半导体装置和树脂片的内模和围绕内模的外模。在操作中，压板首先在解锁状态下与外模接合，以实现相对于内模的精确平行度，并且在锁定压板并熔化树脂片之后，压板进一步向内同时降低外模，使得由下模，外模和用于容纳半导体芯片的压板形成的空间被折叠。

62. 发明授权

US06469370B1 Semiconductor device and method of production of the semiconductor device 失效
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US06469370B1
公开(公告)日：2002-10-22
申请号：US09495332
申请日：2000-02-01
申请人： Toshimi Kawahara , Hirohisa Matsuki , Yasuhiro Shinma , Yoshiyuki Yoneda , Norio Fukasawa , Yuzo Hamanaka , Kenichi Nagashige , Takashi Hozumi
发明人： Toshimi Kawahara , Hirohisa Matsuki , Yasuhiro Shinma , Yoshiyuki Yoneda , Norio Fukasawa , Yuzo Hamanaka , Kenichi Nagashige , Takashi Hozumi
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/3114 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/48 , H01L25/0657 , H01L2224/02375 , H01L2224/0401 , H01L2224/04042 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/16145 , H01L2224/274 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/731 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06572 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： In a semiconductor device of the present invention and a production method thereof, an electronic circuit is provided in a semiconductor substrate, the electronic circuit having terminals. An internal wiring pattern is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals. A protective layer is provided on the substrate, the protective layer covering the substrate. Vias are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate. An external wiring pattern is provided on the protective layer, the external wiring pattern being connected to the vias. Projection electrodes are connected to the external wiring pattern, the projection electrodes having a predetermined height above the external wiring pattern. An enclosure layer of a resin material is provided on the protective layer, the enclosure layer covering sides of the projection electrodes and external surfaces of the external wiring pattern.
摘要翻译：在本发明的半导体器件及其制造方法中，电子电路设置在半导体衬底中，该电子电路具有端子。内部布线图案设置在基板中，内部布线图案连接到电子电路端子。保护层设置在基板上，保护层覆盖基板。在基板上设置通孔，从保护层突出，通孔在基板的任意位置连接到内部布线图案。外部布线图案设置在保护层上，外部布线图形与通孔相连。投射电极连接到外部布线图案，突起电极在外部布线图案上方具有预定的高度。树脂材料的外壳层设置在保护层上，外壳层覆盖突起电极的侧面和外部布线图案的外表面。

63. 发明授权

US5633532A Semiconductor device interconnection 失效
标题翻译：半导体器件互连
公开(公告)号：US5633532A
公开(公告)日：1997-05-27
申请号：US426074
申请日：1995-04-21
申请人： Tuyosi Sohara , Hirohisa Matsuki , Toshiyuki Kuramochi
发明人： Tuyosi Sohara , Hirohisa Matsuki , Toshiyuki Kuramochi
IPC分类号： H01L25/18 , H01L23/433 , H01L23/498 , H01L23/538 , H01L23/64 , H01L25/04 , H05K1/00 , H05K1/11 , H05K1/16 , H05K3/46 , H01L23/053
CPC分类号： H01L23/49894 , H01L23/433 , H01L23/5384 , H01L23/642 , H05K1/115 , H05K1/162 , H01L2224/16225 , H01L2224/48091 , H01L2224/48464 , H01L24/48 , H01L2924/00014 , H01L2924/19041 , H01L2924/19107 , H05K2201/09236 , H05K2201/09509 , H05K2201/09627 , H05K3/4644 , H05K3/4676
摘要： A semiconductor apparatus includes a semiconductor element and a substrate having a substrate base and a thin-film multilayer interconnection layer formed on the substrate base. The thin-film multilayer interconnection layer has insulating layers and interconnection patterns. The insulating layers and the interconnection patterns are alternately layered. Each of the insulating layers includes a first insulating layer part and a second insulating layer part. A surface of the second insulating layer part is more flat than that of the first insulating layer part, and each of the interconnection patterns is arranged on the surface of the second insulating layer part.
摘要翻译：半导体装置包括半导体元件和具有基板基板和形成在基板基板上的薄膜多层互连层的基板。薄膜多层互连层具有绝缘层和互连图案。绝缘层和互连图案交替层叠。每个绝缘层包括第一绝缘层部分和第二绝缘层部分。第二绝缘层部分的表面比第一绝缘层部分的表面更平坦，并且每个互连图案布置在第二绝缘层部分的表面上。

64. 发明授权

US5065223A Packaged semiconductor device 失效
标题翻译：包装半导体器件
公开(公告)号：US5065223A
公开(公告)日：1991-11-12
申请号：US531457
申请日：1990-05-31
申请人： Hirohisa Matsuki , Shigeki Harada , Masahiro Sugimoto , Toshiki Yoshida
发明人： Hirohisa Matsuki , Shigeki Harada , Masahiro Sugimoto , Toshiki Yoshida
IPC分类号： H01L23/055 , H01L23/367 , H01L23/498
CPC分类号： H01L23/3675 , H01L23/055 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H01L2924/01079
摘要： A semiconductor device includes a semiconductor chip, a substrate for supporting the semiconductor chip, a plurality of terminals provided on the substrate for external connections, a plurality of lead wires provided on the semiconductor chip for connections to the terminals, and a multilevel interconnection structure for connecting the plurality of terminals to the plurality of lead wires on the semiconductor chip. The multilevel interconnection structure includes at least a lower conductor layer provided on the substrate and patterned into a plurality of pattern portions connected electrically to the terminals, an insulator layer provided on the lower conductor layer, and an upper conductor layer provided above the insulator layer. The upper conductor layer is formed with a connection area immediately below the lead wires on the semiconductor chip when the semiconductor chip is mounted on the substrate, the upper conductor layer is patterned in the connection area into a plurality of conductor strips extending parallel with each other in correspondence to the lead wires, the insulator layer is provided with contact holes so as to connect electrically the conductor strips of the upper conductor layer with the pattern portions of the lower conductor layer. In the semiconductor device, each of the pattern portions in the connection area has an edge extending obliquely to the conductor strips of the upper conductor layer wherein the pattern portions are disposed so that a pair of adjacent pattern portions have respective edges opposing with each other and extending parallel with each other with a lateral gap extending therebetween.

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