专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07183172B2 Method of forming silicon-on-insulator (SOI) semiconductor substrate and SOI semiconductor substrate formed thereby 失效
标题翻译：形成绝缘体上硅（SOI）半导体衬底和由此形成的SOI半导体衬底的方法
公开(公告)号：US07183172B2
公开(公告)日：2007-02-27
申请号：US10397447
申请日：2003-03-26
申请人： Jung-Il Lee , Geum-Jong Bae , Ki-Chul Kim , Hwa-Sung Rhee , Sang-Su Kim
发明人： Jung-Il Lee , Geum-Jong Bae , Ki-Chul Kim , Hwa-Sung Rhee , Sang-Su Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76259 , H01L21/76254
摘要： A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.
摘要翻译：提供了一种形成SOI半导体衬底的方法和由此形成的SOI半导体衬底。该方法包括在半导体衬底上顺序地形成掩埋氧化物，扩散阻挡层和SOI层。与掩埋氧化物层相比，扩散阻挡层由具有较低杂质扩散系数的绝缘层形成。扩散阻挡层用于防止注入到SOI层中的杂质扩散到掩埋氧化物层或半导体衬底中。

62. 发明授权

US06750532B2 CMOS semiconductor device and method of manufacturing the same 失效
标题翻译： CMOS半导体器件及其制造方法
公开(公告)号：US06750532B2
公开(公告)日：2004-06-15
申请号：US10336604
申请日：2003-01-03
申请人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
发明人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
IPC分类号： H01L29167
CPC分类号： H01L21/2807 , H01L21/823842
摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.
摘要翻译：在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分中的Ge浓度低于10 ％。

63. 发明授权

US06716689B2 MOS transistor having a T-shaped gate electrode and method for fabricating the same 失效
公开(公告)号：US06716689B2
公开(公告)日：2004-04-06
申请号：US10274035
申请日：2002-10-21
申请人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Sang-Su Kim , Jung-Il Lee
发明人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Sang-Su Kim , Jung-Il Lee
IPC分类号： H01L21338
CPC分类号： H01L29/6653 , H01L21/28114 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A MOS transistor having a T-shaped gate electrode and a method for fabricating the same are provided, wherein the MOS transistor includes a T-shaped gate electrode on a semiconductor substrate; an L-shaped lower spacer disposed at both sides of the gate electrode to cover a top surface of the semiconductor substrate; and low-, mid-, and high-concentration impurity regions formed in the semiconductor substrate of both sides of the gate electrode. The high-concentration impurity region is disposed in the semiconductor substrate next to the lower spacer and the mid-concentration impurity region is disposed between the high- and low-concentration impurity regions. A MOS transistor according to the present invention provides a decrease in a capacitance, a decrease in a channel length, and an increase in a cross-sectional area of the gate electrode. At the same time, the mid-concentration impurity region provides a decrease in a source/drain resistance Rsd.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式