专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20120221773A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120221773A1
公开(公告)日：2012-08-30
申请号：US13404883
申请日：2012-02-24
申请人： Shinichi SHUTO , Takayuki Tamura , Noriyuki Kotani , Hiroyasu Tominaga
发明人： Shinichi SHUTO , Takayuki Tamura , Noriyuki Kotani , Hiroyasu Tominaga
IPC分类号： G06F12/00
CPC分类号： G06F11/1068 , G11C16/3431
摘要： The disclosed invention provides a technique for efficiently avoiding read disturbance. A nonvolatile semiconductor memory device includes a nonvolatile memory unit and a controller that can control refresh processing for rewriting data in a block of blocks assumed to be erasable units in the nonvolatile memory unit into anther block different from the block. The controller sets up a first area and a second area different from the first area in the nonvolatile memory unit and, each time a refresh trigger occurs, executes refresh processing for the first area and the second area, such that a refresh frequency of data in the first area will become higher than a refresh frequency of data in the second area. Thereby, it is possible to efficiently avoid read disturbance when read access is repeated.
摘要翻译：所公开的发明提供了一种有效避免读取干扰的技术。非易失性半导体存储器件包括非易失性存储器单元和控制器，其可以控制刷新处理，以将在非易失性存储器单元中被假定为可擦除单元的块中的数据重写为与该块不同的另一块。所述控制器设置与所述非易失性存储器单元中的所述第一区域不同的第一区域和第二区域，并且每次刷新触发发生时，对所述第一区域和所述第二区域执行刷新处理，第一区域将变得高于第二区域中的数据刷新频率。因此，当重复读取访问时，可以有效地避免读取干扰。

62. 发明授权

US08023325B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
公开(公告)号：US08023325B2
公开(公告)日：2011-09-20
申请号：US13019048
申请日：2011-02-01
申请人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
发明人： Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/30 , G11C2211/5621 , G11C2211/5632 , G11C2211/5634 , G11C2211/5641 , G11C2211/5642
摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

63. 发明申请

US20110197108A1 MEMORY CARD AND MEMORY CONTROLLER 有权
标题翻译：内存卡和内存控制器
公开(公告)号：US20110197108A1
公开(公告)日：2011-08-11
申请号：US13089310
申请日：2011-04-18
申请人： Takayuki Tamura , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
发明人： Takayuki Tamura , Hirofumi Shibuya , Hiroyuki Goto , Shigemasa Shiota
IPC分类号： G06F11/08
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译：存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。

64. 发明授权

US07872148B2 Cage-shaped cyclobutanoic dianhydrides and process for production thereof 有权
标题翻译：笼形环丁酸二酐及其生产方法
公开(公告)号：US07872148B2
公开(公告)日：2011-01-18
申请号：US11665024
申请日：2005-10-18
申请人： Hideo Suzuki , Takayuki Tamura
发明人： Hideo Suzuki , Takayuki Tamura
IPC分类号： C07D493/08
CPC分类号： C07C67/11 , C07C51/09 , C07C51/56 , C07C67/08 , C07C67/12 , C07C67/333 , C07C69/74 , C07C2601/04 , C07D493/04 , C07D493/08 , C07C61/04
摘要： A process which comprises reacting a 1,2,3,4-cyclobutanetetracarboxylic-1,2:3,4-dianhydride [1] with an alcohol [2] in the presence of an acid catalyst to obtain a compound [3], isomerizing the compound [3] with a base catalyst into a compound [4], reacting the compound [4] with an organic acid to obtain a compound [5], and reacting the compound [5] with a dehydrating agent to obtain a 1,2,3,4-cyclobutanetetracarboxylic-1,3:2,4-dianhydride: wherein R1 and R2 are each independently hydrogen, halogeno, alkyl of 1 to 10 carbon atoms, halogenated alkyl of 1 to 10 carbon atoms, cycloalkyl of 3 to 8 carbon atoms, phenyl, or cyano; and R3 is alkyl of 1 to 10 carbon atoms.
摘要翻译：一种方法包括在酸催化剂存在下使1,2,3,4-环丁烷四羧酸-1,2：3,4-二酐[1]与醇[2]反应，得到化合物[3]，异构化化合物[3]与碱催化剂合成化合物[4]，使化合物[4]与有机酸反应，得到化合物[5]，并使化合物[5]与脱水剂反应，得到1， 2,3,4-环丁烷四羧酸-1,3：2,4-二酐：其中R1和R2各自独立地为氢，卤代，1-10个碳原子的烷基，1-10个碳原子的卤代烷基，3〜 8个碳原子，苯基或氰基; 并且R 3是1至10个碳原子的烷基。

65. 发明申请

US20100130755A1 PROCESS FOR PRODUCTION OF COUMARIN DIMER COMPOUND 有权
标题翻译：生产欧司素二聚体化合物的方法
公开(公告)号：US20100130755A1
公开(公告)日：2010-05-27
申请号：US12451213
申请日：2008-04-28
申请人： Hideo Suzuki , Takayuki Tamura
发明人： Hideo Suzuki , Takayuki Tamura
IPC分类号： C07D493/04
CPC分类号： C07D493/04
摘要： There is provided a one-step process for producing a dihydroxy-substituted coumarin dimer compound by a photodimerization reaction of a hydroxy-substituted coumarin compound. The process comprises subjecting a hydroxy-substituted coumarin compound to a photodimerization reaction in a solvent selected from aliphatic ketones having 3 to 10 carbon atoms, aliphatic carboxylic acid esters having 2 to 10 carbon atoms, aliphatic alcohols having 1 to 10 carbon atoms, aliphatic nitriles having 2 to 10 carbon atoms, ethers having 4 to 10 carbon atoms, amides having 3 to 10 carbon atoms, and a mixture thereof to obtain a dihydroxy-substituted coumarin dimer compound.
摘要翻译：提供了通过羟基取代的香豆素化合物的光二聚反应制备二羟基取代的香豆素二聚体化合物的一步法。该方法包括使羟基取代的香豆素化合物在选自具有3至10个碳原子的脂族酮，2至10个碳原子的脂肪族羧酸酯，1至10个碳原子的脂族醇，脂族醇，脂族腈具有2至10个碳原子，具有4至10个碳原子的醚，具有3至10个碳原子的酰胺及其混合物，以获得二羟基取代的香豆素二聚体化合物。

66. 发明申请

US20100021584A1 PROCESS FOR PRODUCING FRUIT WITH ENHANCED y-AMINOBUTYRIC ACID CONTENT 审中-公开
标题翻译：用于生产具有增强的γ-氨基丁酸含量的水果的方法
公开(公告)号：US20100021584A1
公开(公告)日：2010-01-28
申请号：US11992597
申请日：2006-09-27
申请人： Takayuki Tamura , Tetsuhiro Yamazaki , Yumiko Suzuki , Hideki Takase , Toshiyuki Ohkubo , Tomonori Konno
发明人： Takayuki Tamura , Tetsuhiro Yamazaki , Yumiko Suzuki , Hideki Takase , Toshiyuki Ohkubo , Tomonori Konno
IPC分类号： C12G1/00 , A23L2/02 , A23L2/52 , C12H1/00
CPC分类号： A23L2/02 , A23L19/00 , A23L33/10 , A23V2002/00 , C12G1/00 , C12G3/02 , A23V2250/038
摘要： The object of the present invention is to provide a method for manufacturing effectively fruit, fruit juice and alcoholic beverage containing a higher concentration of gamma-aminobutyric acid by a relatively simple operation. A fruit of increased gamma-aminobutyric acid content is manufactured by conducting once, or repeatedly conducting two or more times, an operation comprising anaerobic processing followed by aerobic processing of starting material fruit; and further anaerobically processing said fruit to obtain fruit of greater gamma-aminobutyric acid content than the starting material fruit. A fruit juice and an alcoholic beverage are manufactured with the fruit of increased gamma-aminobutyric acid content.
摘要翻译：本发明的目的是提供一种通过相对简单的操作有效制造含有较高浓度的γ-氨基丁酸的水果，果汁和酒精饮料的方法。通过进行一次或重复进行两次或更多次的包含厌氧处理，然后进行原料水果的需氧处理的操作，制造γ-氨基丁酸含量增加的果实; 进一步厌氧处理所述水果以获得比原料水果更大的γ-氨基丁酸含量的果实。制造果汁和酒精饮料，其具有增加的γ-氨基丁酸含量的果实。

67. 发明申请

US20080055986A1 SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 失效
标题翻译：具有故障细胞的半导体存储器件
公开(公告)号：US20080055986A1
公开(公告)日：2008-03-06
申请号：US11931881
申请日：2007-10-31
申请人： Kunihiro KATAYAMA , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro KATAYAMA , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C29/24
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

68. 发明授权

US07334080B2 Nonvolatile memory with independent access capability to associated buffer 有权
标题翻译：非易失性存储器，具有对相关缓冲区的独立访问能力
公开(公告)号：US07334080B2
公开(公告)日：2008-02-19
申请号：US10510150
申请日：2002-11-15
申请人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
发明人： Yoshinori Takase , Keiichi Yoshida , Takashi Horii , Atsushi Nozoe , Takayuki Tamura , Tomoyuki Fujisawa , Ken Matsubara
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/2022 , G06F2212/7203 , G11C16/06 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.
摘要翻译：非易失性存储设备（1）具有非易失性存储单元（FARY 0至FARY 3），缓冲单元（BMRY 0至BMRY 3）和控制单元（CNT）），并且控制单元可以控制第一访问处理在外部和缓冲单元之间以及从外部分别接收到伪指令之后的非易失性存储单元和缓冲单元之间的第二访问处理。控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元指令从外面发出。因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

69. 发明授权

US07234087B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US07234087B2
公开(公告)日：2007-06-19
申请号：US10748156
申请日：2003-12-31
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G11C11/34
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes sector data in one of the first memory and second memory, and next sector data in the other of the first and second memory. Sector data is read out from one of the first memory and second memory to the host computer, and simultaneously, next sector data is read out from the other of the first memory and second memory, and error detection and correction performed in the error correcting means. During a next cycle, the sector data read out from one of the first memory and second memory is outputted to the host computer, and simultaneously, error detection and error correction of the next sector data read out from one of the first computer and second computer is performed in the error correcting means.
摘要翻译：获得高速存储器访问和使用单个纠错装置的透明错误检测和校正。主计算机将扇区数据写入第一存储器和第二存储器之一，以及第一和第二存储器中的另一个中的下一扇区数据。扇区数据从第一存储器和第二存储器之一读出到主计算机，并且同时从第一存储器和第二存储器中的另一个读出下一个扇区数据，并且在纠错装置中执行错误检测和校正。在下一周期中，将从第一存储器和第二存储器之一读出的扇区数据输出到主计算机，同时，从第一计算机和第二计算机之一读出的下一个扇区数据的错误检测和纠错在纠错装置中执行。

70. 发明申请

US20070101047A1 Memory apparatus and controller 审中-公开
标题翻译：内存设备和控制器
公开(公告)号：US20070101047A1
公开(公告)日：2007-05-03
申请号：US10561795
申请日：2004-12-22
申请人： Kiyoshi Kamiya , Takayuki Tamura , Fumio Hara , Kunihiro Katayama
发明人： Kiyoshi Kamiya , Takayuki Tamura , Fumio Hara , Kunihiro Katayama
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/349 , G06F12/0246 , G11C16/3427
摘要： A memory apparatus having a rewritable nonvolatile memory, and a control circuit. The memory apparatus brings logical addresses into correspondence with physical addresses of the nonvolatile memory and retains a piece of number-of-rewrites information for each logical address. The control circuit can perform a replacement process of a piece of memory information on the nonvolatile memory. In the replacement process, a given logical address judged to have a small number of rewrites based on the number-of-rewrites information is replaced so as to correspond to a different physical address and then data is transferred according to the replacement. Even when data of the logical address smaller in the number of rewrites is assigned to the different physical address, the number of rewrites of the region is still grasped as the number of rewrites of the logical address. The data of the logical address is maintained in a condition such that it can be easily targeted for the rewrite by the replacement process even in the place to which the data is transferred. Thus, a memory cell is made less prone to accumulatively suffering disturb owing to rewrite.
摘要翻译：具有可重写非易失性存储器的存储装置和控制电路。存储装置使逻辑地址与非易失性存储器的物理地址相对应，并且为每个逻辑地址保留一段重写数量的信息。控制电路可以在非易失性存储器上执行一条存储器信息的替换处理。在替换处理中，基于重写信息信息判断为具有少量重写的给定逻辑地址被替换为对应于不同的物理地址，然后根据替换来传送数据。即使将重写次数较小的逻辑地址的数据分配给不同的物理地址，也可以将该区域的重写次数作为逻辑地址的重写次数来掌握。逻辑地址的数据被保持在这样的状态，使得即使在数据被传送到的地方也可以容易地通过替换处理进行重写。因此，由于重写，存储器单元不容易累积地受到干扰。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式