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61. 发明授权

US4993697A Copy sheet stack apparatus 失效
标题翻译：复印纸张装置
公开(公告)号：US4993697A
公开(公告)日：1991-02-19
申请号：US311060
申请日：1989-02-16
申请人： Hiroki Yamashita , Toshio Matsui , Keichi Kinoshita , Kazuhito Ozawa , Wataru Kurahashi , Katsuya Yasuda
发明人： Hiroki Yamashita , Toshio Matsui , Keichi Kinoshita , Kazuhito Ozawa , Wataru Kurahashi , Katsuya Yasuda
IPC分类号： B42C1/12 , G03G15/00
CPC分类号： G03G15/6541 , B42C1/12 , G03G15/6552 , B65H2405/20 , G03G2215/00827
摘要： A copy sheet stack apparatus stacks copy sheets discharged from an image-forming device and binds them be means of a staple. The apparatus comprises a first accommodating device for accommodating copy sheets discharged from the image-forming device, a staple device for binding by way of the staple the copy sheets accommodated into the first accommodating device, a second accommodating device disposed below the first accommodating device to accommodate a bundle of the copy sheets bound be means of the staple, a fall device for making the bundle of the copy sheets bound by way of the staple fall from the first accommodating device to accommodate into the second accommodating device by its own weight, and a guide device disposed between the first accommodating device and the second accommodating device to guide the bundle of the copy sheets fallen from the first accommodating device to the second accommodating device. The guide device has a curl device for curling each bundle of the copy sheets in a direction intersecting perpendicularly to a bundle discharging direction so as to make each bundle thereof get rigid to smooth discharge it.
摘要翻译：复印纸叠装置将从图像形成装置排出的复印纸叠合起来，并将其作为订书钉的装置。该装置包括：第一容纳装置，用于容纳从图像形成装置排出的复印纸;装订装置，用于通过订书钉装订装载到第一容纳装置中的复印纸;装配在第一容纳装置下方的第二容纳装置，容纳一束作为订书钉的装置的复印纸，用于使通过订书钉绑定的复印纸束的捆从第一收纳装置落下以通过其自身的重量容纳到第二收纳装置中的下降装置，以及引导装置，其设置在所述第一容纳装置和所述第二容纳装置之间，以引导所述复印纸的束从所述第一容纳装置落到所述第二容纳装置。引导装置具有卷曲装置，用于沿着与束排出方向垂直的方向卷曲每个复印纸束，以使其每个束具有刚性以使其平滑地排出。

62. 发明授权

US4946153A Paper handling apparatus with a paper stapling function 失效
标题翻译：带有装订功能的纸张处理设备
公开(公告)号：US4946153A
公开(公告)日：1990-08-07
申请号：US216517
申请日：1988-07-08
申请人： Keichi Kinoshita , Hiroki Yamashita , Kazuhito Ozawa , Toshio Matsui
发明人： Keichi Kinoshita , Hiroki Yamashita , Kazuhito Ozawa , Toshio Matsui
IPC分类号： B42B4/00 , B65H31/06 , B65H31/20 , B65H31/36 , B65H37/04 , G03G15/00
CPC分类号： G03G15/6541 , B42B4/00 , B65H31/06 , B65H31/20 , B65H31/36 , B65H37/04 , B65H2301/42146 , B65H2404/1114 , G03G2215/00827
摘要： An apparatus for storing papers ejected from a copying machine or the like and stapling them after alignment, comprises a contacting member which contacts each paper being transported into a stapling tray to urge the paper for alignment in a specified portion, and a plurality of pressing members for pressing the transported papers at the upper portion thereof against the tray, each of the pressing members is individually adapted correspondingly to the sizes of papers. The contact between the contacting member and the papers is relieved when the stapled papers are discharged from the tray. The pressing members are actuated in conjunction with the paper transporting operation correspondingly to the size of papers. The contacting member is arranged at a location less distant from transport rollers for transporting papers into the tray than the length of paper in the direction of transporting paper on the tray.
摘要翻译：一种用于存放从复印机等喷出并在对准后装订的纸张的装置包括：接触构件，其接触被输送到装订托盘中的每个纸张以促使纸张在指定部分中对准;以及多个按压构件为了将其上部的传送的纸张压靠在托盘上，每个按压部件分别适应于纸张的尺寸。当装订纸从托盘排出时，接触构件与纸张之间的接触被释放。按照纸张的尺寸，按压构件与纸张传送操作一起被致动。接触构件布置在远离传送辊的位置处，以便将纸输送到托盘中，而不是纸张沿托盘托盘方向的纸张长度。

63. 发明授权

US08311157B2 Signal recovery circuit 有权
标题翻译：信号恢复电路
公开(公告)号：US08311157B2
公开(公告)日：2012-11-13
申请号：US12320409
申请日：2009-01-26
申请人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
发明人： Koji Fukuda , Hiroki Yamashita , Daisuke Hamano
IPC分类号： H04L27/00
CPC分类号： H03L7/08 , H04L7/0331
摘要： A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.
摘要翻译：提供了能够扩大接收余量的信号恢复电路。信号恢复电路包括例如用于产生时钟信号CLKa，CLKb和CLKc的时钟发生器单元CLK_GEN，窗口宽度控制单元WW_CTL和用于产生相位检测器信号（EARLY，LATE）的时钟数据鉴别器单元CD_JGE 例如数据信号Di脉冲沿进入CLKa和CLKb之间，或在CLKb与CLKc之间进入时钟发生器单元。随着基于这些相位检测信号进行控制以维持CLKa，CLKb，CLKc的总相位的相位差，以防止上述Di边缘的入侵，CLK_GEN还调节CLKa和CLKb之间的相位差，以及基于来自WW_CTL的信号（Sww）的CLKb和CLKc之间的相位差。

64. 发明申请

US20120249217A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20120249217A1
公开(公告)日：2012-10-04
申请号：US13500636
申请日：2010-10-04
申请人： Koji Fukuda , Hiroki Yamashita
发明人： Koji Fukuda , Hiroki Yamashita
IPC分类号： H03K17/687 , H01L25/00 , H01L27/088 , H03K3/01
CPC分类号： H03K19/00384 , H01L27/0207 , H01L27/0629 , H01L27/0811 , H01L27/088
摘要： A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
摘要翻译：通过调整偏移电压来实现高速半导体集成电路器件。例如，虚拟NMOS晶体管MND1（MND1a和MND1b）和MND2（MND2a和MND2b）分别连接到根据差分输入信号Din_p和Din_n操作的NMOS晶体管MN1和MN2的漏极输出。 MND1布置成与MN1相邻，并且MND1a的源极和MN1的漏极共享扩散层。 MND2被布置为与MN2相邻，并且MND2a的源极和MN2的漏极共享扩散层。 MND1和MND2用作用于抑制MN1和MN2的处理变化的虚拟晶体管，此外，它们还用作通过适当地向每个门施加偏移量设置信号OFST来调整偏移电压的装置，以提供一个到MN1或MN2的电容器。

65. 发明授权

US08253461B2 Waveform equalization circuit with pulse width modulation 有权
标题翻译：具有脉冲宽度调制的波形均衡电路
公开(公告)号：US08253461B2
公开(公告)日：2012-08-28
申请号：US12826648
申请日：2010-06-29
申请人： Fumio Yuki , Hiroki Yamashita , Koji Fukuda
发明人： Fumio Yuki , Hiroki Yamashita , Koji Fukuda
IPC分类号： H03K3/017
CPC分类号： H04B3/04
摘要： There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC1a, PWCLC2a, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC1a, PWCC2a, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do1_P, Do1_N, thereby adjusting the pulse width. With the use of such a waveform equalization scheme as above, it is possible to attain reduction in power consumption due to simplification in circuit configuration, and further, use of CMOS circuits will enable power consumption to be held back to a low level.
摘要翻译：提供具有脉冲宽度调制的波形均衡电路，其包括脉冲宽度调整电平生成电路PWCLC1a，PWCLC2a，用于分别基于先前的输入数据单元Din_P，Din_N产生脉冲宽度调整电平VCNT，脉冲用于调整根据VCNT的脉冲宽度的宽度调整电路PWCC1a，PWCC2a以及用于整形来自每个脉冲宽度调节电路的输出信号的波形的波形整形电路WAC。脉冲宽度调整电路具有根据前述各输入数据单元的连续比特数进行控制的驱动功率，并且改变每个输出数据单元Do1_P，Do1_N的转换时间，从而调整脉冲宽度。通过使用如上所述的这种波形均衡方案，由于电路结构的简化，可以实现功耗的降低，此外，使用CMOS电路将能够将功耗抑制到低水平。

66. 发明授权

US08037543B2 Image processing apparatus, image processing method, computer program and computer-readable recording medium 有权
标题翻译：图像处理装置，图像处理方法，计算机程序和计算机可读记录介质
公开(公告)号：US08037543B2
公开(公告)日：2011-10-11
申请号：US12753273
申请日：2010-04-02
申请人： Satoru Wakao , Hiroki Yamashita
发明人： Satoru Wakao , Hiroki Yamashita
IPC分类号： G06F7/04
CPC分类号： H04N1/32128 , H04L9/3242 , H04L9/3247 , H04L2209/60 , H04N1/32112 , H04N2201/3233 , H04N2201/3242 , H04N2201/325
摘要： An image processing apparatus includes an alteration unit and a control unit. The alteration unit alters a first image file stored in a removable storage medium in order to generate a second image file. The control unit controls to store the second image file in the storage medium without deleting the first image file from the storage medium, if the first image file includes authentication data that is used to authenticate whether the first image file has been altered.
摘要翻译：图像处理装置包括改变单元和控制单元。改变单元改变存储在可移动存储介质中的第一图像文件，以便生成第二图像文件。如果第一图像文件包括用于认证第一图像文件是否被改变的认证数据，则控制单元控制将第二图像文件存储在存储介质中，而不从存储介质中删除第一图像文件。

67. 发明申请

US20110193595A1 OUTPUT DRIVER CIRCUIT 有权
标题翻译：输出驱动电路
公开(公告)号：US20110193595A1
公开(公告)日：2011-08-11
申请号：US12987092
申请日：2011-01-08
申请人： Koji FUKUDA , Hiroki Yamashita
发明人： Koji FUKUDA , Hiroki Yamashita
IPC分类号： H03K3/00
CPC分类号： H03K5/151 , H03K19/01721 , H04L25/0272 , H04L25/0278 , H04L25/0282 , H04L25/0286 , H04L25/03878
摘要： Disclosed is an output driver circuit capable of realizing reduction in power consumption, and/or enhancement in transmission waveform quality in addition to an increase in transmission speed. The output driver circuit is provided with, for example, a voltage-signal generation circuit block VSG_BK for driving positive negative output-nodes (TXP, TXN) by voltage, -pulse-signal generation circuits PGEN1, PGEN 2 for generating a pulse signal upon a transition of data input signals DIN_P, DIN_N, and current-signal generation circuit blocks ISG_BKp1, ISG_BKn1, for driving TXP, TXN by current for the duration of a pulse width of the pulse-signal. The current-signal generation circuit block executes high-speed charging of parasitic capacitors Cp1, Cp2, occurring to TXP, TXN, respectively, while executing charging of parasitic capacitors Cp1, Cp2, occurring to impedance Z0 respectively. VSG_BK decides a voltage level at TXP, TXN, in the stationary state, keeping TXP, TXN as terminal nodes at impedance Z0, respectively.
摘要翻译：公开了除了传输速度的提高之外，还能够实现功率消耗的降低和/或传输波形质量的提高。输出驱动电路例如具有用于通过电压驱动正负输出节点（TXP，TXN）的电压信号生成电路块VSG_BK，用于产生脉冲信号的脉冲信号生成电路PGEN1，PGEN2 数据输入信号DIN_P，DIN_N和电流信号产生电路块ISG_BKp1，ISG_BKn1的转换，用于在脉冲信号的脉冲宽度的持续时间内通过电流驱动TXP，TXN。电流信号发生电路块分别对发生在阻抗Z0上的寄生电容器Cp1，Cp2进行充电，分别执行对TXP，TXN发生的寄生电容器Cp1，Cp2的高速充电。在固定状态下，VSG_BK决定TXP，TXN的电压电平，分别将TXP，TXN作为终端节点保持在阻抗Z0。

68. 发明授权

US07830167B2 Pre-emphasis circuit 有权
标题翻译：预加重电路
公开(公告)号：US07830167B2
公开(公告)日：2010-11-09
申请号：US12453981
申请日：2009-05-28
申请人： Goichi Ono , Hiroki Yamashita
发明人： Goichi Ono , Hiroki Yamashita
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0272
摘要： A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.
摘要翻译：提供了可以以低成本提高数据传输的通信质量的预加重电路。电流开关电路，电流加法器电路和转移检测电路设置在数据传输系统的发射机中。转移检测电路检测作为差分对的发送数据信号的转变。电流开关电路接收发送数据信号，根据发送数据信号传送驱动电流，并输出作为差分对的输出数据信号。电流加法器电路接收来自转换检测电路的检测信号，并根据检测信号将驱动电流加到负载电阻上。通过这种方式，将转换强调的输出数据信号输入到传输线。

69. 发明申请

US20090033431A1 Oscillation Circuit 审中-公开
标题翻译：振荡电路
公开(公告)号：US20090033431A1
公开(公告)日：2009-02-05
申请号：US12182171
申请日：2008-07-30
申请人： Hiroki Yamashita , Koji Fukuda , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
发明人： Hiroki Yamashita , Koji Fukuda , Ryo Nemoto , Hisaaki Kanai , Keiichi Yamamoto
IPC分类号： H03K3/03
CPC分类号： H03K3/0322
摘要： The present invention provides a highly accurate oscillation circuit. For example, the oscillation circuit includes plural ring oscillator units RO1 and RO2 including inverter circuits IV of an odd number of stages, and an adding unit ADD that adds signals of output nodes RO—01 and RO—02 of the RO1 and RO2. It outputs an addition result of the ADD from an output node OSC_O as a clock signal, and feeds the output node OSC_O back to input nodes RO_I1 and RO_I2 of the RO1 and RO2. Thereby, for example, when each of delay times of the RO1 and RO2 disperses based on a normal distribution of standard deviation σ, the dispersion of a clock signal obtained from the OSC_O can be confined to σ/√{square root over (2)}.
摘要翻译：本发明提供了一种高精度的振荡电路。例如，振荡电路包括包含奇数级的反相器电路IV的多个环形振荡器单元RO1和RO2，以及将RO1和RO2的输出节点RO-01和RO-02的信号相加的相加单元ADD。它从输出节点OSC_O输出ADD的相加结果作为时钟信号，并将输出节点OSC_O反馈给RO1和RO2的输入节点RO_I1和RO_I2。因此，例如，当RO1和RO2的每个延迟时间基于标准偏差Σ的正态分布而分散时，从OSC_O获得的时钟信号的色散可以被限制为sigma /√{ }。

70. 发明授权

US07457850B1 Information server system 失效
标题翻译：信息服务器系统
公开(公告)号：US07457850B1
公开(公告)日：2008-11-25
申请号：US09717019
申请日：2000-11-22
申请人： Kazunori Ukigawa , Hiroki Yamashita
发明人： Kazunori Ukigawa , Hiroki Yamashita
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L67/325
摘要： A server device, which has a content storage section, a content provider, a program table provider, a request processor and the like and can be accessed by a plurality of client devices, is arranged on the Internet. The content provider has a list, in which information about contents with relevance to their transmission times are registered. The content provider reads out the contents from the content storage section based on the list. The request processor controls the content provider to sent the read contents to a client device which has sent a request for transmission of the contents. The program table provider provides the client device, whose request is processed by the request processor, with a program table storing classifications of contents with relevance to their corresponding transmission times. This program table includes information for setting reservation for transmission of contents. The client device, which has received the program table, inputs a request for transmission of contents in accordance with the program table, makes the server device to send the contents to the client device, and makes the server device to send the contents at a time which is reserved and set as transmission time in accordance with the program table.
摘要翻译：具有内容存储部分，内容提供商，节目表提供商，请求处理器等并且可被多个客户端设备访问的服务器设备被布置在因特网上。内容提供者具有列表，其中记录了与其传输时间相关的内容的信息。内容提供者根据列表从内容存储部分读出内容。请求处理器控制内容提供商将读取的内容发送给发送了内容传输请求的客户端设备。程序表提供者向请求处理器处理其请求的客户端设备提供存储与其相应传输时间相关的内容分类的程序表。该程序表包括用于设置内容传输预约的信息。已经接收到节目表的客户端设备根据节目表输入内容传输请求，使得服务器设备将内容发送给客户端设备，并使服务器设备一次发送内容根据程序表保留并设置为传输时间。

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