专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07085917B2 Multi-pipe dispatch and execution of complex instructions in a superscalar processor 有权
标题翻译：超标量处理器中的多管调度和复杂指令的执行
公开(公告)号：US07085917B2
公开(公告)日：2006-08-01
申请号：US10435983
申请日：2003-05-12
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr. , Timothy J. Slegel
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr. , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/325 , G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system, a method and apparatus for dispatching and executing multi-cycle and complex instructions. The method results in maximum performance for such without impacting other areas in the processor such as decode, grouping or dispatch units. This invention allows multi-cycle and complex instructions to be dispatched to one port but executed in multiple execution pipes without cracking the instruction and without limiting it to a single execution pipe. Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). The FXU logic then execute these instructions on the available FXU pipes. This method results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译：在计算机系统中，用于调度和执行多周期和复杂指令的方法和装置。该方法导致最大的性能，而不会影响处理器中的其他区域，如解码，分组或调度单元。本发明允许将多周期和复杂指令分派到一个端口，但是在多个执行管道中执行，而不会破坏指令，而不限于单个执行管道。在调度单元中生成一些控制信号，并通过指令发送到定点单元（FXU）。然后，FXU逻辑在可用的FXU管道上执行这些说明。这种方法导致最佳性能，很少或没有其他并发症。所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。

62. 发明授权

US09280398B2 Major branch instructions 有权
公开(公告)号：US09280398B2
公开(公告)日：2016-03-08
申请号：US13362574
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/52 , G06F9/38 , G06F9/32
CPC分类号： G06F9/528 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3804 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

63. 发明授权

US08914431B2 Range check based lookup tables 有权
标题翻译：基于范围检查的查找表
公开(公告)号：US08914431B2
公开(公告)日：2014-12-16
申请号：US13342232
申请日：2012-01-03
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/38
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.
摘要翻译：提供了利用减少的查找表电路在数据处理装置中执行操作的机制。输入第一输入值，用于从缩小的查找表电路中选择值的子集。缩小的查找表电路仅存储来自对应于缩小的查找表电路的完全填充查找表的边界单元值。值的子集仅包括对应于第一输入值的边界单元值的子集。输入第二值，并且通过缩小查找表电路将第二值与边界单元值子集中的每个边界单元值进行比较。缩小查找表电路基于第二值与边界单元值子集中的每个边界单元值的比较的结果来输出输出值。

64. 发明授权

US08904246B2 Variable acknowledge rate to reduce bus contention in presence of communication errors 有权
标题翻译：在存在通信错误的情况下减少总线争用的可变确认速率
公开(公告)号：US08904246B2
公开(公告)日：2014-12-02
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

65. 发明授权

US08904100B2 Process identifier-based cache data transfer 有权
标题翻译：基于进程标识符的缓存数据传输
公开(公告)号：US08904100B2
公开(公告)日：2014-12-02
申请号：US13493636
申请日：2012-06-11
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/02
CPC分类号： G06F17/30982 , G06F12/0817 , G06F12/12
摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.
摘要翻译：本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

66. 发明申请

US20130339802A1 DYNAMIC HARDWARE TRACE SUPPORTING MULTIPHASE OPERATIONS 有权
标题翻译：动态硬件跟踪支持多种操作
公开(公告)号：US20130339802A1
公开(公告)日：2013-12-19
申请号：US13525054
申请日：2012-06-15
申请人： Steven R. Carlough , Juergen Haess , Michael K. Kroener , Silvia M. Mueller
发明人： Steven R. Carlough , Juergen Haess , Michael K. Kroener , Silvia M. Mueller
IPC分类号： G06F11/34
CPC分类号： G06F11/3476 , G06F11/34 , G06F11/348 , G06F11/3636
摘要： A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals.
摘要翻译：一种用于在数据处理系统中进行跟踪的方法和系统。该方法包括在执行操作期间接收与操作相关联的多个信号。该方法还包括响应于操作是多相操作的指示，在执行操作期间，选择逻辑在多相操作的第一阶段期间，选择和输出作为跟踪信号的多个信号，并且在所述多相操作的第二阶段期间，选择并输出所述多个信号的第二信号作为所述跟踪信号。

67. 发明申请

US20130290802A1 VARIABLE ACKNOWLEDGE RATE TO REDUCE BUS CONTENTION IN PRESENCE OF COMMUNICATION ERRORS 有权
标题翻译：在通信错误存在的情况下，可降低总线容量的可变确认值
公开(公告)号：US20130290802A1
公开(公告)日：2013-10-31
申请号：US13458522
申请日：2012-04-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： H03M13/00 , G06F11/08
CPC分类号： H04L1/08 , H04L1/1864 , H04L2001/0094
摘要： A variable write back indicator control is provided to control the amount of data to be re-transmitted when a packet error occurs. A hardware controller obtains an indication that an acknowledge rate or an amount of set write back indicators of a data frame is to be adjusted. The indication is based on an error rate of data transmission over a communication bus. Based on obtaining the indication that the amount of set write back indicators is to be adjusted, one or more write back indicators are adjusted.
摘要翻译：提供可变写回指示器控件来控制发生数据包错误时要重新发送的数据量。硬件控制器获得要调整数据帧的确认速率或设置回写指示符量的指示。该指示基于通过通信总线的数据传输的错误率。基于获取设定回写指示器的数量的指示，调整一个或多个回写指示符。

68. 发明授权

US08554822B2 Decimal adder with end around carry 失效
标题翻译：十进制加法器结束周围进位
公开(公告)号：US08554822B2
公开(公告)日：2013-10-08
申请号：US12822919
申请日：2010-06-24
申请人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
发明人： Steven R. Carlough , Adam B. Collura , Klaus M. Kroener , Silvia M. Mueller
IPC分类号： G06F7/494
CPC分类号： G06F7/494 , G06F7/508
摘要： Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps.
摘要翻译：对于与BCD数量不同的两个BCD号码的二进制码十进制（BCD）算术加法/减法操作包括响应于BCD算术加/减操作作为减法运算，对第一个BCD运算执行BCD运算减法运算 BCD号和第二BCD号，第一BCD号具有第一幅值，第二BCD号具有第二幅值。第一幅度大于等于或小于第二幅度。执行包括：与进位生成并行，第一和第二BCD号码的部分和或部分差异是计算机，使得基于携带信息的部分和或差异可以从签名幅度形式中选择最终结果，而不进行任何后处理脚步。

69. 发明申请

US20130173683A1 Range Check Based Lookup Tables 有权
公开(公告)号：US20130173683A1
公开(公告)日：2013-07-04
申请号：US13608189
申请日：2012-09-10
申请人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
发明人： Steven R. Carlough , Klaus M. Kroener , Christophe J. Layer , Silvia Melitta Mueller , Kerstin Schelm
IPC分类号： G06F7/535 , G06F12/00
CPC分类号： G06F7/5375 , G06F2207/5354
摘要： Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values.

70. 发明申请

US20110131266A1 Decimal Floating Point Multiplier and Design Structure 失效
标题翻译：十进制浮点乘数和设计结构
公开(公告)号：US20110131266A1
公开(公告)日：2011-06-02
申请号：US12629081
申请日：2009-12-02
申请人： Steven R. Carlough , Daniel Lipetz , Joshua M. Weinberg
发明人： Steven R. Carlough , Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme.
摘要翻译：使用BCD 4221编码方案的小数乘法的几种实现和设计结构，部分乘积的单独积累，部分乘积的累积到最终产品以及从BCD 8421编码方案的转换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式