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61. 发明申请

US20120320004A1 SEMICONDUCTOR DEVICE, ACTIVE MATRIX SUBSTRATE, AND DISPLAY DEVICE 有权
标题翻译：半导体器件，有源矩阵衬底和显示器件
公开(公告)号：US20120320004A1
公开(公告)日：2012-12-20
申请号：US13520853
申请日：2010-09-24
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： H01L29/94 , H01L33/08 , G02F1/1335 , G06F3/038
CPC分类号： H01L27/1251 , G02F1/1334 , G02F1/13624 , G02F1/1368 , G09G3/3648 , G09G2300/0814 , G09G2300/0819 , G09G2300/0852 , G09G2320/0214 , G09G2320/041 , G09G2330/021 , G09G2340/0435 , G09G2360/144 , H01L27/1214 , H01L29/78633 , H01L29/78645
摘要： A switching circuit (semiconductor device) (18) includes two switching units (SW1 and SW2), which are connected in series to each other, and two capacitances (CS1 and CS2), where one electrode of one of the capacitances is connected to the connecting section of the switching units (SW1 and SW2) and one electrode of the other capacitance is connected to one end of the switching units (SW1 and SW2). To the other electrodes of the capacitances (CS1 and CS2), signals having a constant voltage or signals having a same phase are supplied. A bottom gate electrode (light-shielding film) (22) is formed for the switching unit (SW2).
摘要翻译：开关电路（半导体器件）（18）包括彼此串联连接的两个开关单元（SW1和SW2）和两个电容（CS1和CS2），其中一个电容的一个电极连接到开关单元（SW1和SW2）的连接部分和另一个电容的一个电极连接到开关单元（SW1和SW2）的一端。对于电容（CS1和CS2）的其他电极，提供具有恒定电压的信号或具有相同相位的信号。为开关单元（SW2）形成底栅电极（遮光膜）（22）。

62. 发明授权

US08174053B2 Semiconductor device, production method thereof, and electronic device 有权
标题翻译：半导体装置及其制造方法以及电子装置
公开(公告)号：US08174053B2
公开(公告)日：2012-05-08
申请号：US12438394
申请日：2007-06-04
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： H01L29/10
CPC分类号： H01L29/78627 , H01L27/1255 , H01L29/78603 , H01L29/78621
摘要： The present invention provides a semiconductor device which includes a thin film transistor as a resistance element, wherein a variation in resistance of the thin film transistor is suppressed without increasing an area of the resistance element and the resistance element can be produced through simplified production steps. The semiconductor device of the present invention is a semiconductor device including a first thin film transistor and a second thin film transistor on a substrate, the first thin film transistor being used as a resistance element, the second thin film transistor including a semiconductor layer having a low concentration drain region and a high concentration drain region, the low concentration drain region and the high concentration drain region being different in impurity concentration, wherein an impurity concentration of a channel region of a semiconductor layer in the first thin film transistor is the same as an impurity concentration of the low concentration drain region of the semiconductor layer in the second thin film transistor.
摘要翻译：本发明提供一种半导体器件，其包括作为电阻元件的薄膜晶体管，其中抑制薄膜晶体管的电阻变化而不增加电阻元件的面积，并且可以通过简化的制造步骤来制造电阻元件。本发明的半导体器件是在衬底上包括第一薄膜晶体管和第二薄膜晶体管的半导体器件，第一薄膜晶体管用作电阻元件，第二薄膜晶体管包括具有低浓度漏极区域和高浓度漏极区域，低浓度漏极区域和高浓度漏极区域的杂质浓度不同，其中第一薄膜晶体管中的半导体层的沟道区域的杂质浓度与第二薄膜晶体管中的半导体层的低浓度漏极区的杂质浓度。

63. 发明申请

US20100110320A1 DISPLAY DEVICE SUBSTRATE, DISPLAY DEVICE, AND WIRING SUBSTRATE 有权
标题翻译：显示装置基板，显示装置和布线基板
公开(公告)号：US20100110320A1
公开(公告)日：2010-05-06
申请号：US12530557
申请日：2007-12-19
申请人： Hidehito Kitakado
发明人： Hidehito Kitakado
IPC分类号： G02F1/1343
CPC分类号： G02F1/136286 , G02F1/136213 , H01L27/124 , H01L27/3276 , H01L29/78645
摘要： The present invention provides a display device substrate, a display device, and a wiring substrate, each permitting more flexible wiring design and a reduction in area of wirings with suppressing wiring defects.The present invention is a display device substrate including, on a main surface of a substrate, a structure of alternating layers of: a plurality of interlayer insulating films; and three or more wiring layers, wherein the display device substrate includes a data wiring, and the data wiring is positioned in a third or higher wiring layer from a side of the substrate.
摘要翻译：本发明提供了一种显示装置基板，显示装置和布线基板，每个都允许更灵活的布线设计和布线面积的减小，同时抑制布线缺陷。本发明是一种显示装置基板，在基板的主表面上具有交替层的结构：多个层间绝缘膜; 以及三个以上的布线层，其中，所述显示装置用基板包括数据布线，所述数据布线位于从所述基板侧的第三以上布线层。

64. 发明授权

US07202149B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07202149B2
公开(公告)日：2007-04-10
申请号：US11010389
申请日：2004-12-14
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

65. 发明申请

US20070034874A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070034874A1
公开(公告)日：2007-02-15
申请号：US11584524
申请日：2006-10-23
申请人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
发明人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
IPC分类号： H01L29/04 , H01L21/84
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1259 , H01L29/6675 , H01L29/78621 , H01L29/78648
摘要： A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.
摘要翻译：公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 向这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域之上; 和这些层间绝缘膜的开口部分25b，以便位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 以及在第二层间绝缘膜上的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

66. 发明申请

US20050082537A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050082537A1
公开(公告)日：2005-04-21
申请号：US10963822
申请日：2004-10-14
申请人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
发明人： Tatsuya Arao , Takeshi Noda , Takuya Matsuo , Hidehito Kitakado , Masanori Kyoho
IPC分类号： G02F1/1343 , G02F1/1368 , H01L21/20 , H01L21/28 , H01L21/336 , H01L21/77 , H01L21/86 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/04
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1259 , H01L29/6675 , H01L29/78621 , H01L29/78648
摘要： A semiconductor device that can be manufactured with a reduced cost by decreasing the number of masks is disclosed, and a method for manufacturing the semiconductor device is disclosed. The method for manufacturing the semiconductor device comprises the steps of: forming a semiconductor layer 3 having a source and a drain regions 10, 11, and LDD regions 16, 17; a gate insulating film 5; and a gate electrode 6; forming a first and a second interlayer insulating films 24, 25 over the gate electrode 6 and the gate insulating film 5; forming contact holes 25a, 25c to these interlayer insulating films so as to be located over each of the source region and the drain region; and an opening portion 25b to these interlayer insulating films so as to be located over the gate electrode and the LDD region; forming a second gate electrode 26b by a conductive film in the opening portion so as to cover the gate electrode and the LDD region; and a pixel electrode 26a over the second interlayer insulating film; removing the gate insulating film in the contact hole; and forming wirings 27, 28 connected to each the source region and the drain region.
摘要翻译：公开了可以通过减少掩模数而降低成本的半导体器件，并且公开了一种用于制造半导体器件的方法。制造半导体器件的方法包括以下步骤：形成具有源极和漏极区域10,11以及LDD区域16,17的半导体层3; 栅极绝缘膜5; 和栅电极6; 在栅极电极6和栅极绝缘膜5上形成第一和第二层间绝缘膜24,25; 向这些层间绝缘膜形成接触孔25a，25c，以便位于源极区域和漏极区域之上; 和这些层间绝缘膜的开口部分25b，以便位于栅电极和LDD区之上; 通过开口部中的导电膜形成第二栅电极26b，以覆盖栅电极和LDD区; 以及在第二层间绝缘膜上的像素电极26a; 去除接触孔中的栅极绝缘膜; 以及形成连接到每个源极区域和漏极区域的布线27,28。

67. 发明授权

US06346730B1 Liquid crystal display device having a pixel TFT formed in a display region and a drive circuit formed in the periphery of the display region on the same substrate 有权
标题翻译：具有形成在显示区域中的像素TFT的液晶显示装置和形成在同一基板上的显示区域周围的驱动电路
公开(公告)号：US06346730B1
公开(公告)日：2002-02-12
申请号：US09541608
申请日：2000-04-03
申请人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
发明人： Hidehito Kitakado , Ritsuko Kawasaki , Kenji Kasahara
IPC分类号： H01L2701
CPC分类号： H01L29/66765 , G02F1/13454 , H01L27/124 , H01L27/1255 , H01L29/42384 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78627 , H01L29/78633
摘要： The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.
摘要翻译：本发明提供了一种半导体器件，其中布置在每个电路中的底栅TFT或反向交错TFT适当地构成为与各个电路的功能一致，从而提高了半导体器件的工作效率和可靠性。在该结构中，像素TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的N沟道TFT中的LDD区域布置成不与沟道保护绝缘膜重叠，并且通过其至少一部分与栅电极重叠。驱动电路的P沟道TFT中的LDD区域布置成与沟道保护绝缘膜重叠并与栅电极重叠。

68. 发明申请

US20120115286A1 THIN-FILM TRANSISTOR PRODUCING METHOD 有权
标题翻译：薄膜晶体管生产方法
公开(公告)号：US20120115286A1
公开(公告)日：2012-05-10
申请号：US13382448
申请日：2010-02-17
申请人： Tokuaki Kuniyoshi , Hidehito Kitakado , Tadayoshi Miyamoto , Kazuhide Tomiyasu , Sumio Katoh
发明人： Tokuaki Kuniyoshi , Hidehito Kitakado , Tadayoshi Miyamoto , Kazuhide Tomiyasu , Sumio Katoh
IPC分类号： H01L21/336
CPC分类号： H01L29/78621 , G02F1/1368 , H01L29/4908 , H01L29/66765
摘要： Provided is a thin film transistor manufacture method by which a thin film transistor provided with LDD regions can be produced without increasing the number of photo masks used. An etching stopper layer (35) formed on a polycrystalline silicon film (26) of a TFT (10) is used not only as a mask to protect a channel region (27) when a source electrode and a drain electrode are formed by etching, but also as a mask when ions are implanted to form a source/drain regions (39). Thus, phosphorus, which is ion-implanted in the polycrystalline silicon film (26) to form the source/drain regions (39), is not implanted in the LDD region (38) and, accordingly, it is not necessary to additionally form a resist pattern to be used as a mask when ions are implanted.
摘要翻译：提供了一种薄膜晶体管制造方法，通过该方法可以制造具有LDD区的薄膜晶体管，而不增加所使用的光掩模的数量。形成在TFT（10）的多晶硅膜（26）上的蚀刻停止层（35）不仅用作掩模以在通过蚀刻形成源电极和漏电极时保护沟道区（27）而且当离子被注入以形成源/漏区（39）时也作为掩模。因此，离子注入多晶硅膜（26）中以形成源极/漏极区（39）的磷未被植入LDD区（38）中，因此不需要另外形成当植入离子时用作掩模的抗蚀剂图案。

69. 发明授权

US07714367B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714367B2
公开(公告)日：2010-05-11
申请号：US11694467
申请日：2007-03-30
申请人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
发明人： Saishi Fujikawa , Etsuko Asano , Tatsuya Arao , Takashi Yokoshima , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/78621 , H01L27/1237 , H01L29/42384 , H01L29/49 , H01L29/66757
摘要： A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.
摘要翻译：通过一次掺杂杂质可以简化制造步骤的半导体器件及其制造方法。半导体器件的制造方法包括以下步骤：在衬底上形成第一和第二半导体层，在第一和第二半导体层上形成第一绝缘膜，在其上形成第一和第二导电膜，形成具有将第一导电膜的一部分从第二导电膜露出的第一导电膜和第二导电膜的第一绝缘膜在第一绝缘膜之上形成第二绝缘膜，在其上形成第三和第四导电膜，并且形成第二栅电极，其具有第三导电膜和第四导电膜的堆叠层，其中第三导电膜的一部分从第四导电膜暴露在第二半导体层上，其间插入第一绝缘膜和第二绝缘膜。

70. 发明授权

US07276402B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07276402B2
公开(公告)日：2007-10-02
申请号：US11012171
申请日：2004-12-16
申请人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
发明人： Hideto Ohnuma , Masayuki Sakakura , Yasuhiro Mitani , Takuya Matsuo , Hidehito Kitakado
IPC分类号： H01L21/84
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02667 , H01L21/02672 , H01L21/02686 , H01L27/12 , H01L27/1277
摘要： A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof. A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.
摘要翻译：具有抑制空腔制造的结晶半导体膜的半导体器件及其制造方法。根据本发明的半导体器件的制造方法包括以下步骤：在具有绝缘表面的衬底上形成非晶硅膜，向非晶硅膜中添加用于促进结晶的Ni等金属元素，进行热处理，使结晶非晶硅膜，使得在基板上形成结晶硅膜，通过含有机溶剂和氟化物的溶液进行热处理，除去形成在结晶硅膜表面的氧化硅膜，并照射激光或强力光结晶硅膜。

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