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61. 发明授权

US07326616B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07326616B2
公开(公告)日：2008-02-05
申请号：US11717716
申请日：2007-03-14
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first or control gate electrode of a memory cell and leaving the first conductive film over the peripheral circuit forming region, forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least a side wall of the first conductive pattern, and followed by the formation of a gate electrode of a peripheral circuit transistor by etching the first conductive film in the peripheral circuit forming region.
摘要翻译：一种用于IC器件的制造技术，包括在存储单元形成区域上形成第一导体膜并在半导体衬底的外围电路形成区域上形成第一导电膜，形成位于存储单元形成区域上的第一导电膜，以形成第一导电图案，用作存储单元的第一或控制栅极，并将第一导电膜留在外围电路形成区域上，在外围电路形成区域中的存储单元形成区域和第一导电膜上形成第二导电膜，蚀刻所述第二导电膜在所述第一导电图案的至少一个侧壁上形成所述存储单元的第二或存储栅电极，随后通过蚀刻所述第一导电膜中的所述第一导电膜形成外围电路晶体管的栅电极外围电路形成区域。

62. 发明申请

US20070290275A1 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
公开(公告)号：US20070290275A1
公开(公告)日：2007-12-20
申请号：US11822474
申请日：2007-07-06
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L27/088
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

63. 发明申请

US20070155103A1 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070155103A1
公开(公告)日：2007-07-05
申请号：US11717716
申请日：2007-03-14
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： Manufacturing technique for an IC device which includes forming the first conductor film over a memory cell forming region and over a peripheral circuit forming region of a semiconductor substrate, patterning the first conductive film lying over the memory cell forming region to form a first conductive pattern which serves as a first or control gate electrode of a memory cell and leaving the first conductive film over the peripheral circuit forming region, forming a second conductive film over both the memory cell forming region and the first conductive film in the peripheral circuit forming region, etching the second conductive film to form a second or memory gate electrode of the memory cell on at least a side wall of the first conductive pattern, and followed by the formation of a gate electrode of a peripheral circuit transistor by etching the first conductive film in the peripheral circuit forming region.
摘要翻译：一种用于IC器件的制造技术，包括在存储单元形成区域上形成第一导体膜并在半导体衬底的外围电路形成区域上形成第一导电膜，形成位于存储单元形成区域上的第一导电膜，以形成第一导电图案，用作存储单元的第一或控制栅极，并将第一导电膜留在外围电路形成区域上，在外围电路形成区域中的存储单元形成区域和第一导电膜上形成第二导电膜，蚀刻所述第二导电膜在所述第一导电图案的至少一个侧壁上形成所述存储单元的第二或存储栅电极，随后通过蚀刻所述第一导电膜中的所述第一导电膜形成外围电路晶体管的栅电极外围电路形成区域。

64. 发明申请

US20060273406A1 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
公开(公告)号：US20060273406A1
公开(公告)日：2006-12-07
申请号：US11505296
申请日：2006-08-17
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L29/94
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

65. 发明授权

US07067875B2 Semiconductor integrated circuit device and its manufacturing method 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07067875B2
公开(公告)日：2006-06-27
申请号：US10487336
申请日：2002-04-24
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7926
摘要： A semiconductor integrated circuit device has a plurality of rows of pillars, each row being composed of semiconductor pillars and insulator pillars alternately arranged in one direction with no gap therebetween, a plurality of nonvolatile memory elements provided individually in the plurality of semiconductor pillars, the plurality of nonvolatile memory elements having control gate electrodes provided over side surfaces of said semiconductor pillars along the one direction via gate insulating films, drain regions provided in upper surface portions of the semiconductor pillars, and source regions provided in bottom surface portions of the semiconductor pillars, and lines including the respective control gate electrodes of the plurality of nonvolatile memory elements and provided along the one direction over the side surfaces of the rows of pillars along the one direction.
摘要翻译：半导体集成电路器件具有多排支柱，每行由半导体柱和绝缘体柱组成，其一个方向上交替布置，没有间隙，多个非易失性存储元件单独设置在多个半导体柱中，多个具有通过栅极绝缘膜沿着一个方向设置在所述半导体柱的侧表面上的控制栅极的非易失性存储元件，设置在半导体柱的上表面部分中的漏极区域和设置在半导体柱的底表面部分中的源极区域，以及包括多个非易失性存储元件的各个控制栅极电极的线，并且沿着一个方向在支柱列的侧表面上沿着一个方向设置。

66. 发明申请

US20060008992A1 Semiconductor integrated circuit device and a method of manufacturing the same 有权
公开(公告)号：US20060008992A1
公开(公告)日：2006-01-12
申请号：US11212707
申请日：2005-08-29
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： The memory cell transistor includes, in a first well region, a pair of memory electrodes, one of which serves as source electrode and the other serves as drain electrode and a channel region interposed between the pair of memory electrodes. There is, on a channel region, a first gate electrode disposed near its corresponding memory electrode with an insulating film interposed therebetween, and a second gate electrode disposed through insulating films and a charge storage region and electrically isolated from the first gate electrode. A first negative voltage is applied to the first well region to form a state of reverse bias greater than or equal to a junction withstand voltage between the second gate electrode and the memory electrode near the second gate electrode, thereby enabling injection of hot electrons into the charge storage region and injection of electrons from the well region to the charge storage region.

67. 发明授权

US06908837B2 Method of manufacturing a semiconductor integrated circuit device including a gate electrode having a salicide layer thereon 有权
标题翻译：一种半导体集成电路器件的制造方法，其包括在其上具有自对准硅层的栅电极
公开(公告)号：US06908837B2
公开(公告)日：2005-06-21
申请号：US10251849
申请日：2002-09-23
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L27/04 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/8247 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/78 , H01L21/44
CPC分类号： H01L27/0922 , H01L21/26513 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823857 , H01L21/823864 , H01L27/105 , H01L27/10814 , H01L27/10894 , H01L27/11546 , H01L29/1083 , H01L29/665 , H01L29/7833 , H01L29/7835 , Y10S438/981
摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of depositing a first insulating film over a first conductive layer, patterning the first insulating film by using a resist film as a mask to form a cap film, and removing the resist film. After which, a gate electrode of a MISFET is formed by etching the first conductive layer using the cap film as a mask. A second insulating film is deposited over the gate electrode and the cap film and a side wall spacer formed on side surfaces of the gate electrode by etching the second insulating film. After which, a salicide layer is selectively formed on the gate electrode. The cap film is removed by over-etching the first insulating film to etch the cap film.
摘要翻译：一种制造半导体集成电路器件的方法包括以下步骤：在第一导电层上沉积第一绝缘膜，通过使用抗蚀剂膜作为掩模来图案化第一绝缘膜以形成盖膜，并除去抗蚀剂膜。之后，通过使用盖膜作为掩模蚀刻第一导电层来形成MISFET的栅电极。通过蚀刻第二绝缘膜，在栅电极和盖膜上沉积第二绝缘膜和形成在栅电极的侧表面上的侧壁间隔物。之后，在栅电极上选择性地形成自对准硅层。通过对第一绝缘膜进行过蚀刻来去除帽膜以蚀刻帽膜。

68. 发明授权

US06867092B2 Semiconductor integrated circuit device and the process of manufacturing the same for reducing the size of a memory cell by making the width of a bit line than a predetermined minimum size 有权
标题翻译：半导体集成电路器件及其制造方法，用于通过使位线的宽度大于预定的最小尺寸来减小存储器单元的尺寸
公开(公告)号：US06867092B2
公开(公告)日：2005-03-15
申请号：US10013475
申请日：2001-12-13
申请人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
发明人： Hiroyuki Uchiyama , Atsushi Ogishima , Shoji Shukuri
IPC分类号： H01L21/768 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/76 , H01L21/20
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/115 , H01L27/11526
摘要： A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.
摘要翻译：通过使位线的宽度比由光刻的分辨率的极限决定的最小尺寸更窄，DRAM的存储单元的尺寸减小。通过在形成于氧化硅膜中的布线沟槽的内壁上形成氧化硅膜，并且在氧化硅膜内部形成位线，使位线变细。沉积形成在沟槽中的氧化硅膜，使得氧化硅膜具有比布线沟槽的宽度的一半更薄的厚度，并且在氧化硅膜内部的微细间隙中埋入金属膜作为位的材料线。

69. 发明授权

US06661712B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 有权
公开(公告)号：US06661712B2
公开(公告)日：2003-12-09
申请号：US10379545
申请日：2003-03-06
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

70. 发明授权

US06611458B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06611458B2
公开(公告)日：2003-08-26
申请号：US09780393
申请日：2001-02-12
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C1606
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件，通过第一层多晶硅或非易失性存储元件在对半导体集成电路进行测试时被编程，从而在形成非易失性存储元件时不需要特殊工艺，也就是说，可以在形成CMOS器件和器件的过程中形成非易失性存储元件用于编程的激光束不需要，因为在测试中进行编程，可以缩短编程所需的时间，因此可以降低测试成本。

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