专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US06603219B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06603219B2
公开(公告)日：2003-08-05
申请号：US09801472
申请日：2001-03-08
申请人： Masaomi Toyama , Shiro Dosho , Naoshi Yanagisawa
发明人： Masaomi Toyama , Shiro Dosho , Naoshi Yanagisawa
IPC分类号： H02J100
CPC分类号： H03K17/005 , H01L24/06 , H01L2224/05554 , H01L2224/49175 , H01L2924/14 , H03K3/03 , H03K17/693 , Y10T307/391 , Y10T307/461 , Y10T307/492 , H01L2924/00
摘要： A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.
摘要翻译：半导体集成电路包括多个单元。每个单元包括电源焊盘，功能电路和电源控制电路。所述多个单元各自具有第一状态，其中所述功能电路处于处于规定操作电位的所述功率电路处于工作状态，以及所述功能电路通过所述电源处于非工作状态的第二状态垫处于规定的非操作电位。电源控制电路包括用于将电源焊盘连接到规定的非工作电位的开关电路。当多个单元中的至少一个处于第一状态时，多个单元中的每个单元中的电源控制电路闭合开关电路，否则打开开关电路。

62. 发明申请

US20120262320A1 RESONATOR, DELTA-SIGMA MODULATOR, AND WIRELESS COMMUNICATION DEVICE 有权
标题翻译：谐振器，DELTA-SIGMA调制器和无线通信设备
公开(公告)号：US20120262320A1
公开(公告)日：2012-10-18
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
IPC分类号： H03M3/02 , H03F3/45
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译：两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件连接在每个中间节点和信号输入端子之间。并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。

63. 发明授权

US07523154B2 Write compensation circuit and signal interpolation circuit of recording device 有权
标题翻译：写记录装置的补偿电路和信号插补电路
公开(公告)号：US07523154B2
公开(公告)日：2009-04-21
申请号：US11198950
申请日：2005-08-08
申请人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G06G7/00
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译：记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。

64. 发明授权

US07271648B2 Ladder filter, analog equalizer and signal readout system 有权
标题翻译：梯形滤波器，模拟均衡器和信号读出系统
公开(公告)号：US07271648B2
公开(公告)日：2007-09-18
申请号：US10680129
申请日：2003-10-08
申请人： Shiro Dosho , Takashi Morie
发明人： Shiro Dosho , Takashi Morie
IPC分类号： H03K5/00
CPC分类号： G11B20/10009 , H03H11/04 , H03H11/486 , H03H11/50
摘要： A ladder filter includes multiple inductor sections, each including voltage-controlled current sources and capacitors. A second signal input terminal is provided for the filter separately from an ordinary signal input terminal and a signal, which has been input through the second terminal, is supplied to one of the voltage-controlled current sources by way of a gain calculator. By adjusting the gain obtained by the gain calculator to an appropriate value, the ladder filter can make the numerator of its transfer function freely definable.
摘要翻译：梯形滤波器包括多个电感器部分，每个电路部分包括压控电流源和电容器。与普通信号输入端分开设置用于滤波器的第二信号输入端子，并且已经通过第二端子输入的信号通过增益计算器提供给一个压控电流源。通过将增益计算器获得的增益调整到适当的值，梯形滤波器可以使其传递函数的分子自由定义。

65. 发明授权

US07254507B2 Analog circuit automatic calibration system 有权
标题翻译：模拟电路自动校准系统
公开(公告)号：US07254507B2
公开(公告)日：2007-08-07
申请号：US10915345
申请日：2004-08-11
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara
IPC分类号： G01R35/02
CPC分类号： G01R35/005 , G01R31/316
摘要： An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.
摘要翻译：一种模拟电路自动校准系统，用于校准作为具有随着输入设定值变化的特性的模拟电路的目标电路。该系统包括：设定值存储部分，用于存储值并将该值输出到对象电路作为设定值; 用于检测所述目标电路的特性的特性检测部分; 用于确定所述设定值使得所述对象电路的特性被优化的第一特征变化部分; 第二特征变化部，使用与第一特征变化部中使用的算法不同的算法来更新设定值，使得保持对象电路的特性; 以及选择器，用于选择第一和第二特征部分的输出之一，以使所选择的一个存储在设定值存储部分中。

66. 发明授权

US07145379B2 Current driver and display device 有权
标题翻译：当前驱动和显示设备
公开(公告)号：US07145379B2
公开(公告)日：2006-12-05
申请号：US10815800
申请日：2004-04-02
申请人： Yoshito Date , Tetsuro Omori , Shiro Dosho , Makoto Mizuki
发明人： Yoshito Date , Tetsuro Omori , Shiro Dosho , Makoto Mizuki
IPC分类号： H03K17/687 , G09G3/36
CPC分类号： G09G3/3283 , G09G3/3241 , G09G2310/027 , G09G2320/0233 , G09G2330/028
摘要： The first and second chips are provided side by side. The first chip includes: a current supply section for outputting a drive current, the current supply section including a current mirror; a current distribution MISFET; a current input MISFET for transmitting an electric current to the current supply section, the current input MISFET being connected to the current distribution MISFET; and a second current distribution MISFET. The current distribution MISFET and the second current distribution MISFET constitute a current mirror. The second chip includes a second current input MISFET which is connected to the second current distribution MISFET. The ratio between the W/L ratio of the current distribution MISFET and the W/L ratio of the current input MISFET connected thereto is the same in the first and second chips.
摘要翻译：第一和第二芯片并排设置。第一芯片包括：电流供应部分，用于输出驱动电流;电流供应部分包括电流镜; 电流分布MISFET; 电流输入MISFET，用于将电流传输到电流供应部分，电流输入MISFET连接到电流分布MISFET; 和第二电流分布MISFET。电流分布MISFET和第二电流分布MISFET构成电流镜。第二芯片包括连接到第二电流分布MISFET的第二电流输入MISFET。电流分布MISFET的W / L比与与其连接的电流输入MISFET的W / L比之间的比率在第一和第二芯片中是相同的。

67. 发明申请

US20060049973A1 Pipelined A/D converter and method for correcting output of the same 审中-公开
标题翻译：流水线A / D转换器及其输出校正方法
公开(公告)号：US20060049973A1
公开(公告)日：2006-03-09
申请号：US11218784
申请日：2005-09-06
申请人： Shiro Dosho , Takashi Morie
发明人： Shiro Dosho , Takashi Morie
IPC分类号： H03M1/38
CPC分类号： H03M1/1038 , H03M1/168
摘要： Analog inputs to a controllable stage can be switched by an input selecting section, while digital inputs to a D/A converter in the controllable stage can also be switched. An error calculation section calculates an error in the output of the pipelined A/D converter caused by an error in the analog output of the controllable stage, based on the output of the pipelined A/D converter produced when the controllable stage is in a given input state, and an expected value thereof. A correction value generation section generates a correction value for correcting the output of the pipelined A/D converter, based on the calculated error. An output correction section corrects the output of a digital calculation section based on the generated correction value.
摘要翻译：可以通过输入选择部分切换到可控级的模拟输入，而可控切换到D / A转换器的数字输入也可以切换。误差计算部分基于在可控级在给定的时间内产生的流水线A / D转换器的输出，计算由可控级的模拟输出中的误差引起的流水线A / D转换器的输出中的误差输入状态及其期望值。校正值生成部基于计算出的误差来生成校正流水线式A / D转换器的输出的校正值。输出校正部根据生成的校正值来校正数字计算部的输出。

68. 发明授权

US06970313B1 Write compensation circuit and signal interpolation circuit of recording device 失效
标题翻译：写记录装置的补偿电路和信号插补电路
公开(公告)号：US06970313B1
公开(公告)日：2005-11-29
申请号：US09539206
申请日：2000-03-30
申请人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
发明人： Hirokuni Fujiyama , Shiro Dosho , Hiroyuki Nakahira , Akira Yamamoto , Hiroki Mouri
IPC分类号： G11B5/00 , G11B5/09 , G11B20/10 , H03K5/08 , H03K5/13
CPC分类号： G11B20/10 , G11B5/09 , G11B20/10194 , G11B20/10212 , G11B2005/0005 , H03K5/082 , H03K5/13 , H03K5/133
摘要： A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.
摘要翻译：记录装置的写补偿电路包括由第一驱动电压驱动的第一延迟部分，用于接收时钟信号，延迟时钟信号第一延迟时间，并输出延迟时钟信号;以及电压提供部分，用于提供第一驱动电压到第一延迟部分，使得第一延迟时间基本上等于时钟信号的时钟周期。

69. 发明授权

US06556073B2 Transconductor and filter circuit 有权
公开(公告)号：US06556073B2
公开(公告)日：2003-04-29
申请号：US10238107
申请日：2002-09-09
申请人： Takashi Morie , Shiro Dosho
发明人： Takashi Morie , Shiro Dosho
IPC分类号： H04B110
CPC分类号： H03H11/0472 , H03F3/45995 , H03F3/72 , H03H11/0444
摘要： A transconductor which has a transconductance gm and which receives an input voltage Vin and outputs in response to the input voltage Vin an output current Iout of gm×Vin, wherein: the transconductor includes a plurality of sub-transconductors which are connected in parallel to one another; and at least one control signal is input to the plurality of sub-transconductors, and the plurality of sub-transconductors are controlled by the at least one control signal such that at least one of the plurality of sub-transconductors has a negative transconductance, whereby the transconductance gm of the transconductor can be varied.

70. 发明授权

US06466273B1 Analog FIFO memory device 失效
标题翻译：模拟FIFO存储器件
公开(公告)号：US06466273B1
公开(公告)日：2002-10-15
申请号：US09076848
申请日：1998-05-13
申请人： Shiro Dosho , Naoshi Yanagisawa
发明人： Shiro Dosho , Naoshi Yanagisawa
IPC分类号： H04N52136
CPC分类号： G06J1/00
摘要： An analog FIFO memory device allowing for the suppression of the adverse effects produced by fixed pattern noise, generated inside an analog FIFO memory, on signal components. First and second analog multipliers are respectively provided on the input and output sides of the analog FIFO memory. In synchronism with the inputs/outputs of signals to/from the analog FIFO memory, a non-inverting operation and an inverting operation are alternately and repeatedly performed on the input signals and the output signals. Then, although the signal input/output characteristics of the analog FIFO memory are not changed, the fixed pattern noise generated inside the analog FIFO memory is modulated by the second analog multiplier. As a result, the spectrum of the fixed pattern noise, which originally has a lower frequency, is shifted to have a higher frequency. That is to say, since a signal band can be separated from the fixed pattern noise in terms of frequency, the fixed pattern noise can be eliminated by a low pass filter. Consequently, even when the analog FIFO memory device of the present invention is applied for delaying TV signals, the resulting TV image quality is not deteriorated.
摘要翻译：模拟FIFO存储器件允许抑制由模拟FIFO存储器内部产生的固定模式噪声对信号分量产生的不利影响。第一和第二模拟乘法器分别设置在模拟FIFO存储器的输入和输出侧。与来自/来自模拟FIFO存储器的信号的输入/输出同步，对输入信号和输出信号交替重复执行非反相操作和反相操作。然后，虽然模拟FIFO存储器的信号输入/输出特性没有改变，但在模拟FIFO存储器内产生的固定模式噪声被第二模拟乘法器调制。结果，原来具有较低频率的固定图案噪声的频谱被移位以具有较高的频率。也就是说，由于信号频带可以根据频率与固定模式噪声分离，因此可以通过低通滤波器消除固定模式噪声。因此，即使当本发明的模拟FIFO存储器件用于延迟TV信号时，所得到的TV图像质量也不会恶化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式