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1. 发明授权

US07920002B2 Pulse synthesis circuit 有权
标题翻译：脉冲合成电路
公开(公告)号：US07920002B2
公开(公告)日：2011-04-05
申请号：US12133901
申请日：2008-06-05
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Akinori Matsumoto , Takashi Morie , Kazuaki Sogawa , Yukihiro Sasagawa , Masaya Sumita
IPC分类号： H03K5/01
CPC分类号： H03K5/00006 , H03K5/13
摘要： A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.
摘要翻译： n个第一脉冲信号中的每一个的高电平周期部分或全部与在所有n个第二脉冲信号都处于低电平的期间重叠。 n个第二脉冲信号中的每一个的高电平周期部分地或完全地重叠在所有n个第一脉冲信号处于低电平的时段。 n个第一驱动晶体管中的每一个包括连接到接地节点的源极，连接到第一节点的漏极以及接收相应的一个第一脉冲信号的栅极。 n个第二驱动晶体管中的每一个包括连接到接地节点的源极，连接到第二节点的漏极和接收相应的一个第二脉冲信号的栅极。电流镜电路允许对应于流过第二节点的电流的电流流过第一节点。

2. 发明授权

US07633421B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07633421B2
公开(公告)日：2009-12-15
申请号：US12093252
申请日：2007-07-30
申请人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
发明人： Shiro Dosho , Takashi Morie , Yusuke Tokunaga , Shiro Sakiyama
IPC分类号： H03M1/12
CPC分类号： H03M1/123 , H03M1/1215 , H03M1/56
摘要： An A/D converter includes: a plurality of A/D conversion circuits (10 a, 10b); an input selection section (20) for selecting the A/D conversion circuit that is not executing A/D conversion to supply analog amounts obtained by sample-holding an input signal; and an output selection section (30) for selecting the A/D conversion circuit that is not executing A/D conversion to output digital amounts obtained from the selected one. Each A/D conversion circuit includes: an input memory portion (11) for sequentially storing the supplied analog amounts in a plurality of analog memory elements (111); an A/D conversion portion (12) having a plurality of A/D conversion elements (121) for converting the analog amounts stored in the analog memory elements to digital amounts; and a shift output portion (13), having a plurality of registers (131) receiving the digital amounts from the A/D conversion elements to hold the digital amounts, for shifting and outputting the digital amounts held in the registers.
摘要翻译： A / D转换器包括：多个A / D转换电路（10a，10b）; 输入选择部分（20），用于选择不执行A / D转换的A / D转换电路以提供通过采样保持输入信号获得的模拟量; 以及用于选择不执行A / D转换的A / D转换电路以输出从所选择的数字量获得的数字量的输出选择部分（30）。每个A / D转换电路包括：用于在多个模拟存储器元件（111）中顺序地存储所提供的模拟量的输入存储器部分（11）。具有用于将存储在模拟存储器元件中的模拟量转换为数字量的多个A / D转换元件的A / D转换部分（12）以及移位输出部分（13），具有从A / D转换元件接收数字量以保持数字量的多个寄存器（131），用于移位和输出保存在寄存器中的数字量。

3. 发明申请

US20080169948A1 Filter Adjustment Circuit 有权
标题翻译：过滤器调节电路
公开(公告)号：US20080169948A1
公开(公告)日：2008-07-17
申请号：US11792081
申请日：2005-09-02
申请人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
发明人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
IPC分类号： H03M1/06 , H03H11/04 , H03H11/20 , H03M1/10 , H03H11/12
CPC分类号： H03G5/16 , H03H11/1291 , H03H11/20
摘要： In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
摘要翻译：在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成数字信号。来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

4. 发明授权

US07298219B2 Phase-locked loop circuit 有权
标题翻译：锁相环电路
公开(公告)号：US07298219B2
公开(公告)日：2007-11-20
申请号：US11269742
申请日：2005-11-09
申请人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
发明人： Shiro Dosho , Takashi Morie , Kouji Okamoto , Yuji Yamada , Kazuaki Sogawa
IPC分类号： H03L7/00 , H03L1/02
CPC分类号： H03L7/0995 , H03L7/0898 , H03L7/18 , H03L7/1976
摘要： The phase-locked loop circuit includes a gain setting circuit for setting a gain of a voltage controlled oscillator, and a time-constant setting circuit for setting a time constant, which is determined by the amount of current in a charge pump circuit and a capacitance value of a loop filter. The gain setting circuit sets the gain to a predetermined value, and the time-constant setting circuit sets the time constant to a predetermined value, whereby the loop band width of the phase-locked loop circuit is set to a desired value.
摘要翻译：锁相环电路包括用于设定压控振荡器的增益的增益设定电路和用于设定时间常数的时间常数设定电路，时间常数由电荷泵电路中的电流量和电容环路滤波器的值。增益设定电路将增益设定为预定值，时间常数设定电路将时间常数设定为规定值，由此将锁相环电路的环带宽度设定为期望值。

5. 发明申请

US20110050476A1 INTEGRATOR, RESONATOR, AND OVERSAMPLING A/D CONVERTER 有权
标题翻译：集成器，谐振器和超滤A / D转换器
公开(公告)号：US20110050476A1
公开(公告)日：2011-03-03
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M1/12 , G06G7/18
CPC分类号： H03M3/454 , H03M3/404 , H03M3/43
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译：积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。

6. 发明授权

US07855670B2 A-to-D converter 有权
公开(公告)号：US07855670B2
公开(公告)日：2010-12-21
申请号：US12749277
申请日：2010-03-29
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/66
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

7. 发明授权

US07808295B2 Multiphase level shift system 有权
标题翻译：多相电平转换系统
公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00 , H03F3/66
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

8. 发明申请

US20090134931A1 MULTIPHASE LEVEL SHIFT SYSTEM 有权
标题翻译：多级水平移位系统
公开(公告)号：US20090134931A1
公开(公告)日：2009-05-28
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

9. 发明申请

US20090040089A1 A-TO-D CONVERTER 有权
标题翻译： A转To转换器
公开(公告)号：US20090040089A1
公开(公告)日：2009-02-12
申请号：US12162930
申请日：2007-11-30
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.
摘要翻译：逐次逼近型A到D转换器包括循环D转换器（A），用于将模拟值与D转换器（11）的输出值进行比较的比较器（12），以及存储装置（13），用于顺序地存储比较器（12）的输出值，并以相反的顺序将存储的值提供给D-A转换器（11）。

10. 发明授权

US07477099B2 Filter adjustment circuit 有权
标题翻译：滤波器调节电路
公开(公告)号：US07477099B2
公开(公告)日：2009-01-13
申请号：US11792081
申请日：2005-09-02
申请人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
发明人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
IPC分类号： H03B1/00
CPC分类号： H03G5/16 , H03H11/1291 , H03H11/20
摘要： In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
摘要翻译：在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成数字信号。来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

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